From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mx.groups.io with SMTP id smtpd.web10.40157.1683165351555507439 for ; Wed, 03 May 2023 18:55:51 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=aj3kc8tR; spf=pass (domain: intel.com, ip: 134.134.136.20, mailfrom: zhiguang.liu@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1683165351; x=1714701351; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=+5HV8tkzj4FcycKLMgpuf/pBkWhA3ibzWXC8qcyOK2I=; b=aj3kc8tRvWSG/08HJcjjLBdv5czXfvLJhqn5+GCVDU+X/lxm+66Mb481 g1LK9gfDiZ4p27ny8oaXdTt4M6GuzE8vEjcxIv2qrcB7ud6qWiwyDDEpJ +hFGzwLZbKUJ7Ro+rV+t2oz4gYkYkE493RjHRJga1BbTZP1EEXVx2WHFj XAB5oTSTSNJMdtM+eG518BehcIaLOEjl5CMbL4ZMwosfPOu6IkvNQ3Bx8 5/279wf9IsFTxKKxhqsBtLa9+KedmOg7h6zIfHEWeT2OrSfdPdzvN8NbE BobRY2VAvnoH9q/MkzRL+/+XmxeYJJ9YVoF+VCIEAKgMD2hIteb1CG06m A==; X-IronPort-AV: E=McAfee;i="6600,9927,10699"; a="337955426" X-IronPort-AV: E=Sophos;i="5.99,248,1677571200"; d="scan'208";a="337955426" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 May 2023 18:55:51 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10699"; a="674341453" X-IronPort-AV: E=Sophos;i="5.99,248,1677571200"; d="scan'208";a="674341453" Received: from shwdesfp01.ccr.corp.intel.com ([10.239.158.151]) by orsmga006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 May 2023 18:55:48 -0700 From: "Zhiguang Liu" To: devel@edk2.groups.io Cc: Zhiguang Liu , Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann , Debkumar De , Catharine West Subject: [PATCH v4 5/5] UefiCpuPkg/ResetVector: Support 5 level page table in ResetVector Date: Thu, 4 May 2023 09:55:17 +0800 Message-Id: <20230504015517.2487-6-zhiguang.liu@intel.com> X-Mailer: git-send-email 2.31.1.windows.1 In-Reply-To: <20230504015517.2487-1-zhiguang.liu@intel.com> References: <20230504015517.2487-1-zhiguang.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add a macro USE_5_LEVEL_PAGE_TABLE to determine whether to create 5 level page table. If macro USE_5_LEVEL_PAGE_TABLE is defined, PML5Table is created at (4G-12K), while PML4Table is at (4G-16K). In runtime check, if 5level paging is supported, use PML5Table, otherwise, use PML4Table. If macro USE_5_LEVEL_PAGE_TABLE is not defined, to save space, 5level paging is not created, and 4level paging is at (4G-12K) and be used. Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann Cc: Debkumar De Cc: Catharine West Signed-off-by: Zhiguang Liu --- .../ResetVector/Vtf0/Ia32/Flat32ToFlat64.asm | 25 +++++++++++++++++-- .../ResetVector/Vtf0/Ia32/PageTables64.asm | 24 ------------------ UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb | 1 - .../ResetVector/Vtf0/X64/PageTables.asm | 9 +++++++ 4 files changed, 32 insertions(+), 27 deletions(-) delete mode 100644 UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm diff --git a/UefiCpuPkg/ResetVector/Vtf0/Ia32/Flat32ToFlat64.asm b/UefiCpuPkg/ResetVector/Vtf0/Ia32/Flat32ToFlat64.asm index 6891397c2a..f119f941a5 100644 --- a/UefiCpuPkg/ResetVector/Vtf0/Ia32/Flat32ToFlat64.asm +++ b/UefiCpuPkg/ResetVector/Vtf0/Ia32/Flat32ToFlat64.asm @@ -2,7 +2,7 @@ ; @file ; Transition from 32 bit flat protected mode into 64 bit flat protected mode ; -; Copyright (c) 2008 - 2018, Intel Corporation. All rights reserved.
+; Copyright (c) 2008 - 2023, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent ; ;------------------------------------------------------------------------------ @@ -14,7 +14,28 @@ BITS 32 ; Transition32FlatTo64Flat: - OneTimeCall SetCr3ForPageTables64 +%ifdef USE_5_LEVEL_PAGE_TABLE + mov eax, 0 + cpuid + cmp eax, 07h ; check if basic CPUID leaf contains leaf 07 + jb NotSupport5LevelPaging ; 5level paging not support, downgrade to 4level paging + mov eax, 07h ; check cpuid leaf 7, subleaf 0 + mov ecx, 0 + cpuid + bt ecx, 16 ; [Bits 16] Supports 5-level paging if 1. + jnc NotSupport5LevelPaging ; 5level paging not support, downgrade to 4level paging + mov eax, ADDR_OF(Pml5) + mov cr3, eax + mov eax, cr4 + bts eax, 12 ; Set LA57=1. + mov cr4, eax + jmp SetCr3Done +NotSupport5LevelPaging: +%endif + + mov eax, ADDR_OF(Pml4) + mov cr3, eax +SetCr3Done: mov eax, cr4 bts eax, 5 ; enable PAE diff --git a/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm b/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm deleted file mode 100644 index f188da20ba..0000000000 --- a/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm +++ /dev/null @@ -1,24 +0,0 @@ -;------------------------------------------------------------------------------ -; @file -; Sets the CR3 register for 64-bit paging -; -; Copyright (c) 2008 - 2023, Intel Corporation. All rights reserved.
-; SPDX-License-Identifier: BSD-2-Clause-Patent -; -;------------------------------------------------------------------------------ - -BITS 32 - -; -; Modified: EAX -; -SetCr3ForPageTables64: - - ; - ; These pages are built into the ROM image in X64/PageTables.asm - ; - mov eax, ADDR_OF(Pml4) - mov cr3, eax - - OneTimeCallRet SetCr3ForPageTables64 - diff --git a/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb b/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb index 136361e62c..5a6563bd34 100644 --- a/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb +++ b/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb @@ -54,7 +54,6 @@ %ifdef ARCH_X64 %include "Ia32/Flat32ToFlat64.asm" -%include "Ia32/PageTables64.asm" %endif %include "Ia16/Real16ToFlat32.asm" diff --git a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm index 60f11a1f7d..b89a4efea9 100644 --- a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm +++ b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm @@ -81,4 +81,13 @@ Pml4: ; DQ PAGE_NLE(Pdp) TIMES 0x1000 - ($ - Pml4) DB 0 + +%ifdef USE_5_LEVEL_PAGE_TABLE +Pml5: + ; + ; Pml5 table (only first entry is present, pointing to Pml4) + ; + DQ PAGE_NLE(Pml4) + TIMES 0x1000 - ($ - Pml5) DB 0 +%endif EndOfPageTables: -- 2.31.1.windows.1