[PATCH 1/7] ArmPkg: fix reading of first nibbles in ArmCpuInfo

["Marcin Juszkiewicz" <marcin.juszkiewicz@linaro.org>]

First nibbles of DFR0/ISAR1/ISAR2/MMRF2/PFR0 system registers were read
in wrong way -- second one was used instead.

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
---
 ArmPkg/Application/ArmCpuInfo/ArmCpuInfo.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/ArmPkg/Application/ArmCpuInfo/ArmCpuInfo.c b/ArmPkg/Application/ArmCpuInfo/ArmCpuInfo.c
index deea90fbdfbf..3f0a49649790 100644
--- a/ArmPkg/Application/ArmCpuInfo/ArmCpuInfo.c
+++ b/ArmPkg/Application/ArmCpuInfo/ArmCpuInfo.c
@@ -107,7 +107,7 @@ HandleAa64Dfr0 (
   CONST CHAR8         *Bits;
 
   Bits  = "3:0 ";
-  Value = (Aa64Dfr0 >>  4) & 0xf;
+  Value = Aa64Dfr0 & 0xf;
   switch (Value) {
     case b0110:
       Description = "Armv8 debug architecture";
@@ -637,7 +637,7 @@ HandleAa64Isar1 (
   CONST CHAR8         *Bits;
 
   Bits  = "3:0 ";
-  Value = (Aa64Isar1 >>  4) & 0xf;
+  Value = Aa64Isar1 & 0xf;
   switch (Value) {
     case b0000:
       Description = "DC CVAP not implemented.";
@@ -954,7 +954,7 @@ HandleAa64Isar2 (
   CONST CHAR8         *Bits;
 
   Bits  = "3:0 ";
-  Value = (Aa64Isar2 >>  4) & 0xf;
+  Value = Aa64Isar2 & 0xf;
   switch (Value) {
     case b0000:
       Description = "FEAT_WFxT not implemented.";
@@ -1637,7 +1637,7 @@ HandleAa64Mmfr2 (
   CONST CHAR8         *Bits;
 
   Bits  = "3:0 ";
-  Value = (Aa64Mmfr2)       & 0xf;
+  Value = Aa64Mmfr2 & 0xf;
   switch (Value) {
     case b0000:
       Description = "FEAT_TTCNP not implemented.";
@@ -1906,7 +1906,7 @@ HandleAa64Pfr0 (
   CONST CHAR8         *Bits;
 
   Bits  = "3:0 ";
-  Value = (Aa64Pfr0)       & 0xf;
+  Value = Aa64Pfr0 & 0xf;
   switch (Value) {
     case b0001:
       Description = "EL0 in AArch64 only";
-- 
2.40.1