[edk2-devel][edk2-platforms][PATCH 1/2] AmpereAltraPkg: Add support for PCIe Auto Bifurcation

[Minh Nguyen <minhnguyen1@os.amperecomputing.com>]

From: Vu Nguyen <vunguyen@os.amperecomputing.com>

Add extra option call Auto to the Bifurcation selection. This mode will
automatically select the best bifurcation mode the current Root Complex.
Currently, this option only availabe on the RCA with x16 width.

Signed-off-by: Minh Nguyen <minhnguyen1@os.amperecomputing.com>
---
 Silicon/Ampere/AmpereAltraPkg/Include/Guid/RootComplexInfoHob.h                     |   5 +-
 Silicon/Ampere/AmpereAltraPkg/Library/Ac01PcieLib/PcieCore.h                        |   5 +
 Silicon/Ampere/AmpereAltraPkg/Drivers/PcieInitPei/RootComplexNVParam.c              |   2 +
 Silicon/Ampere/AmpereAltraPkg/Drivers/RootComplexConfigDxe/RootComplexConfigDxe.c   |  12 +-
 Silicon/Ampere/AmpereAltraPkg/Library/Ac01PcieLib/PcieCore.c                        | 344 +++++++++++++++++++-
 Silicon/Ampere/AmpereAltraPkg/Drivers/RootComplexConfigDxe/RootComplexConfigDxe.uni |   3 +-
 6 files changed, 365 insertions(+), 6 deletions(-)

diff --git a/Silicon/Ampere/AmpereAltraPkg/Include/Guid/RootComplexInfoHob.h b/Silicon/Ampere/AmpereAltraPkg/Include/Guid/RootComplexInfoHob.h
index 24599b781646..0b252de37dcc 100644
--- a/Silicon/Ampere/AmpereAltraPkg/Include/Guid/RootComplexInfoHob.h
+++ b/Silicon/Ampere/AmpereAltraPkg/Include/Guid/RootComplexInfoHob.h
@@ -1,6 +1,6 @@
 /** @file
 
-  Copyright (c) 2021, Ampere Computing LLC. All rights reserved.<BR>
+  Copyright (c) 2021 - 2023, Ampere Computing LLC. All rights reserved.<BR>
 
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
@@ -40,7 +40,8 @@ typedef enum {
   DevMapMode2,
   DevMapMode3,
   DevMapMode4,
-  MaxDevMapMode = DevMapMode4
+  DevMapModeAuto,
+  MaxDevMapMode = DevMapModeAuto
 } DEV_MAP_MODE;
 
 //
diff --git a/Silicon/Ampere/AmpereAltraPkg/Library/Ac01PcieLib/PcieCore.h b/Silicon/Ampere/AmpereAltraPkg/Library/Ac01PcieLib/PcieCore.h
index a18fff7dbb75..988450a54260 100644
--- a/Silicon/Ampere/AmpereAltraPkg/Library/Ac01PcieLib/PcieCore.h
+++ b/Silicon/Ampere/AmpereAltraPkg/Library/Ac01PcieLib/PcieCore.h
@@ -46,6 +46,11 @@
 #define PFA_MODE_CLEAR                   1
 #define PFA_MODE_READ                    2
 
+#define BIFURCATION_X000                 0
+#define BIFURCATION_X0X0                 1
+#define BIFURCATION_X0XX                 2
+#define BIFURCATION_XXXX                 3
+
 //
 // Host Bridge registers
 //
diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/PcieInitPei/RootComplexNVParam.c b/Silicon/Ampere/AmpereAltraPkg/Drivers/PcieInitPei/RootComplexNVParam.c
index da730c4bd219..08dff0f1311f 100644
--- a/Silicon/Ampere/AmpereAltraPkg/Drivers/PcieInitPei/RootComplexNVParam.c
+++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/PcieInitPei/RootComplexNVParam.c
@@ -128,6 +128,7 @@ SetRootComplexBifurcation (
     RootComplex->Pcie[RPStart + 3].Active = TRUE;
     break;
 
+  case DevMapModeAuto:
   case DevMapMode4:
     MaxWidth = (RootComplex->Type == RootComplexTypeA) ? LINK_WIDTH_X4 : LINK_WIDTH_X2;
     RootComplex->Pcie[RPStart].MaxWidth = PCIE_GET_MAX_WIDTH (RootComplex->Pcie[RPStart], MaxWidth);
@@ -526,6 +527,7 @@ GetMaxSpeedGen (
       }
       break;
 
+    case DevMapModeAuto:
     case DevMapMode4: /* x4 x4 x4 x4 */
       if (RootComplex->Flags & PCIE_ERRATA_SPEED1) {
         MaxGen = ErrataSpeedDevMap4;
diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/RootComplexConfigDxe/RootComplexConfigDxe.c b/Silicon/Ampere/AmpereAltraPkg/Drivers/RootComplexConfigDxe/RootComplexConfigDxe.c
index e03be2a2f9dc..52a297ff085d 100644
--- a/Silicon/Ampere/AmpereAltraPkg/Drivers/RootComplexConfigDxe/RootComplexConfigDxe.c
+++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/RootComplexConfigDxe/RootComplexConfigDxe.c
@@ -1,6 +1,6 @@
 /** @file
 
-  Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.<BR>
+  Copyright (c) 2020 - 2023, Ampere Computing LLC. All rights reserved.<BR>
 
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
@@ -600,6 +600,16 @@ CreateDevMapOptions (
     DevMapMode4
     );
 
+  if (RootComplex->Type == RootComplexTypeA) {
+    HiiCreateOneOfOptionOpCode (
+      OptionsOpCodeHandle,
+      STRING_TOKEN (STR_PCIE_BIFUR_SELECT_AUTO),
+      0,
+      EFI_IFR_NUMERIC_SIZE_1,
+      DevMapModeAuto
+      );
+  }
+
   return OptionsOpCodeHandle;
 }
 
diff --git a/Silicon/Ampere/AmpereAltraPkg/Library/Ac01PcieLib/PcieCore.c b/Silicon/Ampere/AmpereAltraPkg/Library/Ac01PcieLib/PcieCore.c
index 855b094f7948..f7c8defc1906 100644
--- a/Silicon/Ampere/AmpereAltraPkg/Library/Ac01PcieLib/PcieCore.c
+++ b/Silicon/Ampere/AmpereAltraPkg/Library/Ac01PcieLib/PcieCore.c
@@ -664,6 +664,267 @@ EnableDbiAccess (
   MmioWrite32 (TargetAddress, Val);
 }
 
+VOID
+Ac01PcieUpdateMaxWidth (
+  IN AC01_ROOT_COMPLEX   *RootComplex
+  )
+{
+  if (RootComplex->Type == RootComplexTypeA) {
+    switch (RootComplex->DevMapLow) {
+    case DevMapMode1:
+      RootComplex->Pcie[PcieController0].MaxWidth = CAP_MAX_LINK_WIDTH_X16;
+      break;
+
+    case DevMapMode2:
+      RootComplex->Pcie[PcieController0].MaxWidth = CAP_MAX_LINK_WIDTH_X8;
+      RootComplex->Pcie[PcieController2].MaxWidth = CAP_MAX_LINK_WIDTH_X8;
+      break;
+
+    case DevMapMode3:
+      RootComplex->Pcie[PcieController0].MaxWidth = CAP_MAX_LINK_WIDTH_X8;
+      RootComplex->Pcie[PcieController2].MaxWidth = CAP_MAX_LINK_WIDTH_X4;
+      RootComplex->Pcie[PcieController3].MaxWidth = CAP_MAX_LINK_WIDTH_X4;
+      break;
+
+    case DevMapMode4:
+      RootComplex->Pcie[PcieController0].MaxWidth = CAP_MAX_LINK_WIDTH_X4;
+      RootComplex->Pcie[PcieController1].MaxWidth = CAP_MAX_LINK_WIDTH_X4;
+      RootComplex->Pcie[PcieController2].MaxWidth = CAP_MAX_LINK_WIDTH_X4;
+      RootComplex->Pcie[PcieController3].MaxWidth = CAP_MAX_LINK_WIDTH_X4;
+      break;
+
+    default:
+      ASSERT (FALSE);
+    }
+  } else {
+    switch (RootComplex->DevMapLow) {
+    case DevMapMode1:
+      RootComplex->Pcie[PcieController0].MaxWidth = CAP_MAX_LINK_WIDTH_X8;
+      break;
+
+    case DevMapMode2:
+      RootComplex->Pcie[PcieController0].MaxWidth = CAP_MAX_LINK_WIDTH_X4;
+      RootComplex->Pcie[PcieController2].MaxWidth = CAP_MAX_LINK_WIDTH_X4;
+      break;
+
+    case DevMapMode3:
+      RootComplex->Pcie[PcieController0].MaxWidth = CAP_MAX_LINK_WIDTH_X4;
+      RootComplex->Pcie[PcieController2].MaxWidth = CAP_MAX_LINK_WIDTH_X2;
+      RootComplex->Pcie[PcieController3].MaxWidth = CAP_MAX_LINK_WIDTH_X2;
+      break;
+
+    case DevMapMode4:
+      RootComplex->Pcie[PcieController0].MaxWidth = CAP_MAX_LINK_WIDTH_X2;
+      RootComplex->Pcie[PcieController1].MaxWidth = CAP_MAX_LINK_WIDTH_X2;
+      RootComplex->Pcie[PcieController2].MaxWidth = CAP_MAX_LINK_WIDTH_X2;
+      RootComplex->Pcie[PcieController3].MaxWidth = CAP_MAX_LINK_WIDTH_X2;
+      break;
+
+    default:
+      ASSERT (FALSE);
+    }
+
+    switch (RootComplex->DevMapHigh) {
+    case DevMapMode1:
+      RootComplex->Pcie[PcieController4].MaxWidth = CAP_MAX_LINK_WIDTH_X8;
+      break;
+
+    case DevMapMode2:
+      RootComplex->Pcie[PcieController4].MaxWidth = CAP_MAX_LINK_WIDTH_X4;
+      RootComplex->Pcie[PcieController6].MaxWidth = CAP_MAX_LINK_WIDTH_X4;
+      break;
+
+    case DevMapMode3:
+      RootComplex->Pcie[PcieController4].MaxWidth = CAP_MAX_LINK_WIDTH_X4;
+      RootComplex->Pcie[PcieController6].MaxWidth = CAP_MAX_LINK_WIDTH_X2;
+      RootComplex->Pcie[PcieController7].MaxWidth = CAP_MAX_LINK_WIDTH_X2;
+      break;
+
+    case DevMapMode4:
+      RootComplex->Pcie[PcieController4].MaxWidth = CAP_MAX_LINK_WIDTH_X2;
+      RootComplex->Pcie[PcieController5].MaxWidth = CAP_MAX_LINK_WIDTH_X2;
+      RootComplex->Pcie[PcieController6].MaxWidth = CAP_MAX_LINK_WIDTH_X2;
+      RootComplex->Pcie[PcieController7].MaxWidth = CAP_MAX_LINK_WIDTH_X2;
+      break;
+
+    default:
+      ASSERT (FALSE);
+    }
+  }
+}
+
+VOID
+Ac01PcieUpdateActive (
+  IN AC01_ROOT_COMPLEX   *RootComplex
+  )
+{
+  switch (RootComplex->DevMapLow) {
+  case DevMapMode1:
+    RootComplex->Pcie[PcieController0].Active = TRUE;
+    RootComplex->Pcie[PcieController1].Active = FALSE;
+    RootComplex->Pcie[PcieController2].Active = FALSE;
+    RootComplex->Pcie[PcieController3].Active = FALSE;
+    break;
+
+  case DevMapMode2:
+    RootComplex->Pcie[PcieController0].Active = TRUE;
+    RootComplex->Pcie[PcieController1].Active = FALSE;
+    RootComplex->Pcie[PcieController2].Active = TRUE;
+    RootComplex->Pcie[PcieController3].Active = FALSE;
+    break;
+
+  case DevMapMode3:
+    RootComplex->Pcie[PcieController0].Active = TRUE;
+    RootComplex->Pcie[PcieController1].Active = FALSE;
+    RootComplex->Pcie[PcieController2].Active = TRUE;
+    RootComplex->Pcie[PcieController3].Active = TRUE;
+    break;
+
+  case DevMapMode4:
+    RootComplex->Pcie[PcieController0].Active = TRUE;
+    RootComplex->Pcie[PcieController1].Active = TRUE;
+    RootComplex->Pcie[PcieController2].Active = TRUE;
+    RootComplex->Pcie[PcieController3].Active = TRUE;
+    break;
+
+  default:
+    ASSERT (FALSE);
+  }
+
+  if (RootComplex->Type == RootComplexTypeB) {
+    switch (RootComplex->DevMapHigh) {
+    case DevMapMode1:
+      RootComplex->Pcie[PcieController4].Active = TRUE;
+      RootComplex->Pcie[PcieController5].Active = FALSE;
+      RootComplex->Pcie[PcieController6].Active = FALSE;
+      RootComplex->Pcie[PcieController7].Active = FALSE;
+      break;
+
+    case DevMapMode2:
+      RootComplex->Pcie[PcieController4].Active = TRUE;
+      RootComplex->Pcie[PcieController5].Active = FALSE;
+      RootComplex->Pcie[PcieController6].Active = TRUE;
+      RootComplex->Pcie[PcieController7].Active = FALSE;
+      break;
+
+    case DevMapMode3:
+      RootComplex->Pcie[PcieController4].Active = TRUE;
+      RootComplex->Pcie[PcieController5].Active = FALSE;
+      RootComplex->Pcie[PcieController6].Active = TRUE;
+      RootComplex->Pcie[PcieController7].Active = TRUE;
+      break;
+
+    case DevMapMode4:
+      RootComplex->Pcie[PcieController4].Active = TRUE;
+      RootComplex->Pcie[PcieController5].Active = TRUE;
+      RootComplex->Pcie[PcieController6].Active = TRUE;
+      RootComplex->Pcie[PcieController7].Active = TRUE;
+      break;
+
+    default:
+      ASSERT (FALSE);
+    }
+  }
+}
+
+EFI_STATUS
+Ac01PcieCorrectBifurcation (
+  IN     AC01_ROOT_COMPLEX             *RootComplex,
+  IN     PCI_REG_PCIE_LINK_CAPABILITY  *LinkCap,
+  IN     UINTN                         LinkCapLength,
+  IN OUT DEV_MAP_MODE                  *Bifur
+  )
+{
+  UINTN       Count;
+  UINTN       Idx;
+  EFI_STATUS  Status;
+
+  Status = EFI_SUCCESS;
+
+  if (RootComplex == NULL || LinkCap == NULL || Bifur == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  if (LinkCapLength != 4) {
+    // Only process 4 controller at a same time
+    return EFI_INVALID_PARAMETER;
+  }
+
+  if (LinkCap[PcieController1].Uint32 != 0) {
+    // Bifurcation should be X/X/X/X
+    *Bifur = BIFURCATION_XXXX;
+    return Status;
+  }
+
+  Count = 0;
+  for (Idx = 0; Idx < LinkCapLength; Idx++) {
+    if (LinkCap[Idx].Uint32 != 0) {
+      Count++;
+    }
+  }
+
+  switch (Count) {
+  case 3:
+    // Bifurcation should be X/0/X/X
+    *Bifur = BIFURCATION_X0XX;
+    break;
+
+  case 2:
+    if (LinkCap[PcieController0].Uint32 != 0) {
+      if (LinkCap[PcieController2].Uint32) {
+        *Bifur = BIFURCATION_X0X0;
+      } else {
+        *Bifur = BIFURCATION_X0XX;
+      }
+    } else {
+      *Bifur = BIFURCATION_XXXX;
+    }
+    break;
+
+  case 1:
+    if (LinkCap[PcieController0].Uint32 != 0) {
+      *Bifur = BIFURCATION_X000;
+    } else if (LinkCap[PcieController2].Uint32 != 0) {
+      *Bifur = BIFURCATION_X0X0;
+    } else {
+      // In the lane reverse case, we choose best width
+      switch (LinkCap[PcieController3].Bits.MaxLinkWidth) { /* MAX_SPEED [9:4] */
+      case CAP_MAX_LINK_WIDTH_X1:
+      case CAP_MAX_LINK_WIDTH_X2:
+        *Bifur = BIFURCATION_XXXX;
+        break;
+
+      case CAP_MAX_LINK_WIDTH_X4:
+        if (RootComplex->Type == RootComplexTypeA) {
+          *Bifur = BIFURCATION_XXXX;
+        } else {
+          *Bifur = BIFURCATION_X0X0;
+        }
+        break;
+
+      case CAP_MAX_LINK_WIDTH_X8:
+        if (RootComplex->Type == RootComplexTypeA) {
+          *Bifur = BIFURCATION_X0X0;
+        } else {
+          *Bifur = BIFURCATION_X000;
+        }
+        break;
+
+      default:
+        *Bifur = BIFURCATION_X000;
+        break;
+      }
+    }
+    break;
+
+  default:
+    Status = EFI_NOT_AVAILABLE_YET;
+    break;
+  }
+
+  return Status;
+}
+
 /**
   Setup and initialize the AC01 PCIe Root Complex and underneath PCIe controllers
 
@@ -687,12 +948,87 @@ Ac01PcieCoreSetupRC (
   RETURN_STATUS        Status;
   UINT32               Val;
   UINT8                PcieIndex;
+  BOOLEAN                       AutoLaneBifurcationEnabled = FALSE;
+  PCI_REG_PCIE_LINK_CAPABILITY  LinkCap[MaxPcieController];
+  AC01_PCIE_CONTROLLER          *Pcie;
+  DEV_MAP_MODE                  DevMapMode;
 
   DEBUG ((DEBUG_INFO, "Initializing Socket%d RootComplex%d\n", RootComplex->Socket, RootComplex->ID));
 
-  ProgramHostBridgeInfo (RootComplex);
-
+AutoLaneBifurcationRetry:
   if (!ReInit) {
+    if (AutoLaneBifurcationEnabled) {
+      //
+      // We are here after the first round
+      //
+      // As per 2.7.2. AC Specifications of PCIe card specification this TPVPERL time and
+      // should be minimum 100ms. So this is minimum time we need add and found during test.
+      //
+      MicroSecondDelay (100000);
+      SetMem ((VOID *)LinkCap, sizeof (LinkCap), 0);
+      for (PcieIndex = 0; PcieIndex < RootComplex->MaxPcieController; PcieIndex++) {
+        Pcie = &RootComplex->Pcie[PcieIndex];
+        if (!Pcie->Active || !PcieLinkUpCheck (Pcie)) {
+          continue;
+        }
+        DEBUG ((DEBUG_INFO, "RootComplex->ID:%d Port:%d link up\n", RootComplex->ID, PcieIndex));
+        TargetAddress = GetCapabilityBase (RootComplex, PcieIndex, FALSE, EFI_PCI_CAPABILITY_ID_PCIEXP);
+        if (TargetAddress == 0) {
+          continue;
+        }
+        LinkCap[PcieIndex].Uint32 = MmioRead32 (TargetAddress + LINK_CAPABILITIES_REG);
+      }
+
+      Status = Ac01PcieCorrectBifurcation (RootComplex, LinkCap, MaxPcieControllerOfRootComplexA, &DevMapMode);
+      if (!EFI_ERROR (Status)) {
+        RootComplex->DevMapLow = DevMapMode;
+        DEBUG ((
+          DEBUG_INFO,
+          "RootComplex->ID:%d Auto Bifurcation done, DevMapMode:%d\n",
+          RootComplex->ID,
+          RootComplex->DevMapLow
+          ));
+      } else {
+        RootComplex->DevMapLow = DevMapMode1;
+        DEBUG ((
+          DEBUG_INFO,
+          "RootComplex->ID:%d Auto Bifurcation failed, revert to DevMapMode1\n",
+          RootComplex->ID
+          ));
+      }
+
+      AutoLaneBifurcationEnabled = FALSE;
+
+      if (DevMapMode == DevMapMode4) {
+        // Return directly as the RootComplex already initialized in this mode
+        return EFI_SUCCESS;
+      }
+
+      //
+      // Update the RootComplex data with new DevMapMode
+      //
+      Ac01PcieUpdateActive (RootComplex);
+      Ac01PcieUpdateMaxWidth (RootComplex);
+    } else {
+      if (RootComplex->DevMapLow == DevMapModeAuto) {
+        // Set lowest bifurcation mode
+        RootComplex->DevMapLow = DevMapMode4;
+
+        AutoLaneBifurcationEnabled = TRUE;
+        DEBUG ((
+          DEBUG_INFO,
+          "RootComplex->ID:%d Auto Bifurcation enabled\n",
+          RootComplex->ID
+          ));
+      }
+    }
+
+    ProgramHostBridgeInfo (RootComplex);
+
+    // Fix for UEFI hang due to timing change with bifurcation
+    // register moved very close to PHY initialization.
+    MicroSecondDelay (100000);
+
     Status = PciePhyInit (RootComplex->SerdesBase);
     if (RETURN_ERROR (Status)) {
       DEBUG ((DEBUG_ERROR, "%a: Failed to initialize the PCIe PHY\n", __FUNCTION__));
@@ -855,6 +1191,10 @@ Ac01PcieCoreSetupRC (
     }
   }
 
+  if (AutoLaneBifurcationEnabled) {
+    goto AutoLaneBifurcationRetry;
+  }
+
   return RETURN_SUCCESS;
 }
 
diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/RootComplexConfigDxe/RootComplexConfigDxe.uni b/Silicon/Ampere/AmpereAltraPkg/Drivers/RootComplexConfigDxe/RootComplexConfigDxe.uni
index f28fda05def9..06535a9581e3 100644
--- a/Silicon/Ampere/AmpereAltraPkg/Drivers/RootComplexConfigDxe/RootComplexConfigDxe.uni
+++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/RootComplexConfigDxe/RootComplexConfigDxe.uni
@@ -1,5 +1,5 @@
 //
-// Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.<BR>
+// Copyright (c) 2020 - 2023, Ampere Computing LLC. All rights reserved.<BR>
 //
 // SPDX-License-Identifier: BSD-2-Clause-Patent
 //
@@ -78,6 +78,7 @@
 #string STR_PCIE_RC15_FORM              #language en-US "Root Complex 15 Configuration"
 #string STR_PCIE_RC15_FORM_HELP         #language en-US "Root Complex 15 Configuration"
 
+#string STR_PCIE_BIFUR_SELECT_AUTO      #language en-US "Auto"
 #string STR_PCIE_BIFUR_SELECT_VALUE0    #language en-US "x16"
 #string STR_PCIE_BIFUR_SELECT_VALUE1    #language en-US "x8+x8"
 #string STR_PCIE_BIFUR_SELECT_VALUE2    #language en-US "x8+x4+x4"
-- 
2.39.0