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This mode will automatically select the best bifurcation mode the current Root Complex. Currently, this option only availabe on the RCA with x16 width. Signed-off-by: Minh Nguyen --- Silicon/Ampere/AmpereAltraPkg/Include/Guid/RootComplexInfoHob.h = | 5 +- Silicon/Ampere/AmpereAltraPkg/Library/Ac01PcieLib/PcieCore.h = | 5 + Silicon/Ampere/AmpereAltraPkg/Drivers/PcieInitPei/RootComplexNVParam.c = | 2 + Silicon/Ampere/AmpereAltraPkg/Drivers/RootComplexConfigDxe/RootComplexConf= igDxe.c | 12 +- Silicon/Ampere/AmpereAltraPkg/Library/Ac01PcieLib/PcieCore.c = | 344 +++++++++++++++++++- Silicon/Ampere/AmpereAltraPkg/Drivers/RootComplexConfigDxe/RootComplexConf= igDxe.uni | 3 +- 6 files changed, 365 insertions(+), 6 deletions(-) diff --git a/Silicon/Ampere/AmpereAltraPkg/Include/Guid/RootComplexInfoHob.= h b/Silicon/Ampere/AmpereAltraPkg/Include/Guid/RootComplexInfoHob.h index 24599b781646..0b252de37dcc 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Include/Guid/RootComplexInfoHob.h +++ b/Silicon/Ampere/AmpereAltraPkg/Include/Guid/RootComplexInfoHob.h @@ -1,6 +1,6 @@ /** @file =20 - Copyright (c) 2021, Ampere Computing LLC. All rights reserved.
+ Copyright (c) 2021 - 2023, Ampere Computing LLC. All rights reserved. =20 SPDX-License-Identifier: BSD-2-Clause-Patent =20 @@ -40,7 +40,8 @@ typedef enum { DevMapMode2, DevMapMode3, DevMapMode4, - MaxDevMapMode =3D DevMapMode4 + DevMapModeAuto, + MaxDevMapMode =3D DevMapModeAuto } DEV_MAP_MODE; =20 // diff --git a/Silicon/Ampere/AmpereAltraPkg/Library/Ac01PcieLib/PcieCore.h b= /Silicon/Ampere/AmpereAltraPkg/Library/Ac01PcieLib/PcieCore.h index a18fff7dbb75..988450a54260 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Library/Ac01PcieLib/PcieCore.h +++ b/Silicon/Ampere/AmpereAltraPkg/Library/Ac01PcieLib/PcieCore.h @@ -46,6 +46,11 @@ #define PFA_MODE_CLEAR 1 #define PFA_MODE_READ 2 =20 +#define BIFURCATION_X000 0 +#define BIFURCATION_X0X0 1 +#define BIFURCATION_X0XX 2 +#define BIFURCATION_XXXX 3 + // // Host Bridge registers // diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/PcieInitPei/RootComplexN= VParam.c b/Silicon/Ampere/AmpereAltraPkg/Drivers/PcieInitPei/RootComplexNVP= aram.c index da730c4bd219..08dff0f1311f 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Drivers/PcieInitPei/RootComplexNVParam.= c +++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/PcieInitPei/RootComplexNVParam.= c @@ -128,6 +128,7 @@ SetRootComplexBifurcation ( RootComplex->Pcie[RPStart + 3].Active =3D TRUE; break; =20 + case DevMapModeAuto: case DevMapMode4: MaxWidth =3D (RootComplex->Type =3D=3D RootComplexTypeA) ? LINK_WIDTH_= X4 : LINK_WIDTH_X2; RootComplex->Pcie[RPStart].MaxWidth =3D PCIE_GET_MAX_WIDTH (RootComple= x->Pcie[RPStart], MaxWidth); @@ -526,6 +527,7 @@ GetMaxSpeedGen ( } break; =20 + case DevMapModeAuto: case DevMapMode4: /* x4 x4 x4 x4 */ if (RootComplex->Flags & PCIE_ERRATA_SPEED1) { MaxGen =3D ErrataSpeedDevMap4; diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/RootComplexConfigDxe/Roo= tComplexConfigDxe.c b/Silicon/Ampere/AmpereAltraPkg/Drivers/RootComplexConf= igDxe/RootComplexConfigDxe.c index e03be2a2f9dc..52a297ff085d 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Drivers/RootComplexConfigDxe/RootComple= xConfigDxe.c +++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/RootComplexConfigDxe/RootComple= xConfigDxe.c @@ -1,6 +1,6 @@ /** @file =20 - Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved. + Copyright (c) 2020 - 2023, Ampere Computing LLC. All rights reserved. =20 SPDX-License-Identifier: BSD-2-Clause-Patent =20 @@ -600,6 +600,16 @@ CreateDevMapOptions ( DevMapMode4 ); =20 + if (RootComplex->Type =3D=3D RootComplexTypeA) { + HiiCreateOneOfOptionOpCode ( + OptionsOpCodeHandle, + STRING_TOKEN (STR_PCIE_BIFUR_SELECT_AUTO), + 0, + EFI_IFR_NUMERIC_SIZE_1, + DevMapModeAuto + ); + } + return OptionsOpCodeHandle; } =20 diff --git a/Silicon/Ampere/AmpereAltraPkg/Library/Ac01PcieLib/PcieCore.c b= /Silicon/Ampere/AmpereAltraPkg/Library/Ac01PcieLib/PcieCore.c index 855b094f7948..f7c8defc1906 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Library/Ac01PcieLib/PcieCore.c +++ b/Silicon/Ampere/AmpereAltraPkg/Library/Ac01PcieLib/PcieCore.c @@ -664,6 +664,267 @@ EnableDbiAccess ( MmioWrite32 (TargetAddress, Val); } =20 +VOID +Ac01PcieUpdateMaxWidth ( + IN AC01_ROOT_COMPLEX *RootComplex + ) +{ + if (RootComplex->Type =3D=3D RootComplexTypeA) { + switch (RootComplex->DevMapLow) { + case DevMapMode1: + RootComplex->Pcie[PcieController0].MaxWidth =3D CAP_MAX_LINK_WIDTH_X= 16; + break; + + case DevMapMode2: + RootComplex->Pcie[PcieController0].MaxWidth =3D CAP_MAX_LINK_WIDTH_X= 8; + RootComplex->Pcie[PcieController2].MaxWidth =3D CAP_MAX_LINK_WIDTH_X= 8; + break; + + case DevMapMode3: + RootComplex->Pcie[PcieController0].MaxWidth =3D CAP_MAX_LINK_WIDTH_X= 8; + RootComplex->Pcie[PcieController2].MaxWidth =3D CAP_MAX_LINK_WIDTH_X= 4; + RootComplex->Pcie[PcieController3].MaxWidth =3D CAP_MAX_LINK_WIDTH_X= 4; + break; + + case DevMapMode4: + RootComplex->Pcie[PcieController0].MaxWidth =3D CAP_MAX_LINK_WIDTH_X= 4; + RootComplex->Pcie[PcieController1].MaxWidth =3D CAP_MAX_LINK_WIDTH_X= 4; + RootComplex->Pcie[PcieController2].MaxWidth =3D CAP_MAX_LINK_WIDTH_X= 4; + RootComplex->Pcie[PcieController3].MaxWidth =3D CAP_MAX_LINK_WIDTH_X= 4; + break; + + default: + ASSERT (FALSE); + } + } else { + switch (RootComplex->DevMapLow) { + case DevMapMode1: + RootComplex->Pcie[PcieController0].MaxWidth =3D CAP_MAX_LINK_WIDTH_X= 8; + break; + + case DevMapMode2: + RootComplex->Pcie[PcieController0].MaxWidth =3D CAP_MAX_LINK_WIDTH_X= 4; + RootComplex->Pcie[PcieController2].MaxWidth =3D CAP_MAX_LINK_WIDTH_X= 4; + break; + + case DevMapMode3: + RootComplex->Pcie[PcieController0].MaxWidth =3D CAP_MAX_LINK_WIDTH_X= 4; + RootComplex->Pcie[PcieController2].MaxWidth =3D CAP_MAX_LINK_WIDTH_X= 2; + RootComplex->Pcie[PcieController3].MaxWidth =3D CAP_MAX_LINK_WIDTH_X= 2; + break; + + case DevMapMode4: + RootComplex->Pcie[PcieController0].MaxWidth =3D CAP_MAX_LINK_WIDTH_X= 2; + RootComplex->Pcie[PcieController1].MaxWidth =3D CAP_MAX_LINK_WIDTH_X= 2; + RootComplex->Pcie[PcieController2].MaxWidth =3D CAP_MAX_LINK_WIDTH_X= 2; + RootComplex->Pcie[PcieController3].MaxWidth =3D CAP_MAX_LINK_WIDTH_X= 2; + break; + + default: + ASSERT (FALSE); + } + + switch (RootComplex->DevMapHigh) { + case DevMapMode1: + RootComplex->Pcie[PcieController4].MaxWidth =3D CAP_MAX_LINK_WIDTH_X= 8; + break; + + case DevMapMode2: + RootComplex->Pcie[PcieController4].MaxWidth =3D CAP_MAX_LINK_WIDTH_X= 4; + RootComplex->Pcie[PcieController6].MaxWidth =3D CAP_MAX_LINK_WIDTH_X= 4; + break; + + case DevMapMode3: + RootComplex->Pcie[PcieController4].MaxWidth =3D CAP_MAX_LINK_WIDTH_X= 4; + RootComplex->Pcie[PcieController6].MaxWidth =3D CAP_MAX_LINK_WIDTH_X= 2; + RootComplex->Pcie[PcieController7].MaxWidth =3D CAP_MAX_LINK_WIDTH_X= 2; + break; + + case DevMapMode4: + RootComplex->Pcie[PcieController4].MaxWidth =3D CAP_MAX_LINK_WIDTH_X= 2; + RootComplex->Pcie[PcieController5].MaxWidth =3D CAP_MAX_LINK_WIDTH_X= 2; + RootComplex->Pcie[PcieController6].MaxWidth =3D CAP_MAX_LINK_WIDTH_X= 2; + RootComplex->Pcie[PcieController7].MaxWidth =3D CAP_MAX_LINK_WIDTH_X= 2; + break; + + default: + ASSERT (FALSE); + } + } +} + +VOID +Ac01PcieUpdateActive ( + IN AC01_ROOT_COMPLEX *RootComplex + ) +{ + switch (RootComplex->DevMapLow) { + case DevMapMode1: + RootComplex->Pcie[PcieController0].Active =3D TRUE; + RootComplex->Pcie[PcieController1].Active =3D FALSE; + RootComplex->Pcie[PcieController2].Active =3D FALSE; + RootComplex->Pcie[PcieController3].Active =3D FALSE; + break; + + case DevMapMode2: + RootComplex->Pcie[PcieController0].Active =3D TRUE; + RootComplex->Pcie[PcieController1].Active =3D FALSE; + RootComplex->Pcie[PcieController2].Active =3D TRUE; + RootComplex->Pcie[PcieController3].Active =3D FALSE; + break; + + case DevMapMode3: + RootComplex->Pcie[PcieController0].Active =3D TRUE; + RootComplex->Pcie[PcieController1].Active =3D FALSE; + RootComplex->Pcie[PcieController2].Active =3D TRUE; + RootComplex->Pcie[PcieController3].Active =3D TRUE; + break; + + case DevMapMode4: + RootComplex->Pcie[PcieController0].Active =3D TRUE; + RootComplex->Pcie[PcieController1].Active =3D TRUE; + RootComplex->Pcie[PcieController2].Active =3D TRUE; + RootComplex->Pcie[PcieController3].Active =3D TRUE; + break; + + default: + ASSERT (FALSE); + } + + if (RootComplex->Type =3D=3D RootComplexTypeB) { + switch (RootComplex->DevMapHigh) { + case DevMapMode1: + RootComplex->Pcie[PcieController4].Active =3D TRUE; + RootComplex->Pcie[PcieController5].Active =3D FALSE; + RootComplex->Pcie[PcieController6].Active =3D FALSE; + RootComplex->Pcie[PcieController7].Active =3D FALSE; + break; + + case DevMapMode2: + RootComplex->Pcie[PcieController4].Active =3D TRUE; + RootComplex->Pcie[PcieController5].Active =3D FALSE; + RootComplex->Pcie[PcieController6].Active =3D TRUE; + RootComplex->Pcie[PcieController7].Active =3D FALSE; + break; + + case DevMapMode3: + RootComplex->Pcie[PcieController4].Active =3D TRUE; + RootComplex->Pcie[PcieController5].Active =3D FALSE; + RootComplex->Pcie[PcieController6].Active =3D TRUE; + RootComplex->Pcie[PcieController7].Active =3D TRUE; + break; + + case DevMapMode4: + RootComplex->Pcie[PcieController4].Active =3D TRUE; + RootComplex->Pcie[PcieController5].Active =3D TRUE; + RootComplex->Pcie[PcieController6].Active =3D TRUE; + RootComplex->Pcie[PcieController7].Active =3D TRUE; + break; + + default: + ASSERT (FALSE); + } + } +} + +EFI_STATUS +Ac01PcieCorrectBifurcation ( + IN AC01_ROOT_COMPLEX *RootComplex, + IN PCI_REG_PCIE_LINK_CAPABILITY *LinkCap, + IN UINTN LinkCapLength, + IN OUT DEV_MAP_MODE *Bifur + ) +{ + UINTN Count; + UINTN Idx; + EFI_STATUS Status; + + Status =3D EFI_SUCCESS; + + if (RootComplex =3D=3D NULL || LinkCap =3D=3D NULL || Bifur =3D=3D NULL)= { + return EFI_INVALID_PARAMETER; + } + + if (LinkCapLength !=3D 4) { + // Only process 4 controller at a same time + return EFI_INVALID_PARAMETER; + } + + if (LinkCap[PcieController1].Uint32 !=3D 0) { + // Bifurcation should be X/X/X/X + *Bifur =3D BIFURCATION_XXXX; + return Status; + } + + Count =3D 0; + for (Idx =3D 0; Idx < LinkCapLength; Idx++) { + if (LinkCap[Idx].Uint32 !=3D 0) { + Count++; + } + } + + switch (Count) { + case 3: + // Bifurcation should be X/0/X/X + *Bifur =3D BIFURCATION_X0XX; + break; + + case 2: + if (LinkCap[PcieController0].Uint32 !=3D 0) { + if (LinkCap[PcieController2].Uint32) { + *Bifur =3D BIFURCATION_X0X0; + } else { + *Bifur =3D BIFURCATION_X0XX; + } + } else { + *Bifur =3D BIFURCATION_XXXX; + } + break; + + case 1: + if (LinkCap[PcieController0].Uint32 !=3D 0) { + *Bifur =3D BIFURCATION_X000; + } else if (LinkCap[PcieController2].Uint32 !=3D 0) { + *Bifur =3D BIFURCATION_X0X0; + } else { + // In the lane reverse case, we choose best width + switch (LinkCap[PcieController3].Bits.MaxLinkWidth) { /* MAX_SPEED [= 9:4] */ + case CAP_MAX_LINK_WIDTH_X1: + case CAP_MAX_LINK_WIDTH_X2: + *Bifur =3D BIFURCATION_XXXX; + break; + + case CAP_MAX_LINK_WIDTH_X4: + if (RootComplex->Type =3D=3D RootComplexTypeA) { + *Bifur =3D BIFURCATION_XXXX; + } else { + *Bifur =3D BIFURCATION_X0X0; + } + break; + + case CAP_MAX_LINK_WIDTH_X8: + if (RootComplex->Type =3D=3D RootComplexTypeA) { + *Bifur =3D BIFURCATION_X0X0; + } else { + *Bifur =3D BIFURCATION_X000; + } + break; + + default: + *Bifur =3D BIFURCATION_X000; + break; + } + } + break; + + default: + Status =3D EFI_NOT_AVAILABLE_YET; + break; + } + + return Status; +} + /** Setup and initialize the AC01 PCIe Root Complex and underneath PCIe cont= rollers =20 @@ -687,12 +948,87 @@ Ac01PcieCoreSetupRC ( RETURN_STATUS Status; UINT32 Val; UINT8 PcieIndex; + BOOLEAN AutoLaneBifurcationEnabled =3D FALSE; + PCI_REG_PCIE_LINK_CAPABILITY LinkCap[MaxPcieController]; + AC01_PCIE_CONTROLLER *Pcie; + DEV_MAP_MODE DevMapMode; =20 DEBUG ((DEBUG_INFO, "Initializing Socket%d RootComplex%d\n", RootComplex= ->Socket, RootComplex->ID)); =20 - ProgramHostBridgeInfo (RootComplex); - +AutoLaneBifurcationRetry: if (!ReInit) { + if (AutoLaneBifurcationEnabled) { + // + // We are here after the first round + // + // As per 2.7.2. AC Specifications of PCIe card specification this T= PVPERL time and + // should be minimum 100ms. So this is minimum time we need add and = found during test. + // + MicroSecondDelay (100000); + SetMem ((VOID *)LinkCap, sizeof (LinkCap), 0); + for (PcieIndex =3D 0; PcieIndex < RootComplex->MaxPcieController; Pc= ieIndex++) { + Pcie =3D &RootComplex->Pcie[PcieIndex]; + if (!Pcie->Active || !PcieLinkUpCheck (Pcie)) { + continue; + } + DEBUG ((DEBUG_INFO, "RootComplex->ID:%d Port:%d link up\n", RootCo= mplex->ID, PcieIndex)); + TargetAddress =3D GetCapabilityBase (RootComplex, PcieIndex, FALSE= , EFI_PCI_CAPABILITY_ID_PCIEXP); + if (TargetAddress =3D=3D 0) { + continue; + } + LinkCap[PcieIndex].Uint32 =3D MmioRead32 (TargetAddress + LINK_CAP= ABILITIES_REG); + } + + Status =3D Ac01PcieCorrectBifurcation (RootComplex, LinkCap, MaxPcie= ControllerOfRootComplexA, &DevMapMode); + if (!EFI_ERROR (Status)) { + RootComplex->DevMapLow =3D DevMapMode; + DEBUG (( + DEBUG_INFO, + "RootComplex->ID:%d Auto Bifurcation done, DevMapMode:%d\n", + RootComplex->ID, + RootComplex->DevMapLow + )); + } else { + RootComplex->DevMapLow =3D DevMapMode1; + DEBUG (( + DEBUG_INFO, + "RootComplex->ID:%d Auto Bifurcation failed, revert to DevMapMod= e1\n", + RootComplex->ID + )); + } + + AutoLaneBifurcationEnabled =3D FALSE; + + if (DevMapMode =3D=3D DevMapMode4) { + // Return directly as the RootComplex already initialized in this = mode + return EFI_SUCCESS; + } + + // + // Update the RootComplex data with new DevMapMode + // + Ac01PcieUpdateActive (RootComplex); + Ac01PcieUpdateMaxWidth (RootComplex); + } else { + if (RootComplex->DevMapLow =3D=3D DevMapModeAuto) { + // Set lowest bifurcation mode + RootComplex->DevMapLow =3D DevMapMode4; + + AutoLaneBifurcationEnabled =3D TRUE; + DEBUG (( + DEBUG_INFO, + "RootComplex->ID:%d Auto Bifurcation enabled\n", + RootComplex->ID + )); + } + } + + ProgramHostBridgeInfo (RootComplex); + + // Fix for UEFI hang due to timing change with bifurcation + // register moved very close to PHY initialization. + MicroSecondDelay (100000); + Status =3D PciePhyInit (RootComplex->SerdesBase); if (RETURN_ERROR (Status)) { DEBUG ((DEBUG_ERROR, "%a: Failed to initialize the PCIe PHY\n", __FU= NCTION__)); @@ -855,6 +1191,10 @@ Ac01PcieCoreSetupRC ( } } =20 + if (AutoLaneBifurcationEnabled) { + goto AutoLaneBifurcationRetry; + } + return RETURN_SUCCESS; } =20 diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/RootComplexConfigDxe/Roo= tComplexConfigDxe.uni b/Silicon/Ampere/AmpereAltraPkg/Drivers/RootComplexCo= nfigDxe/RootComplexConfigDxe.uni index f28fda05def9..06535a9581e3 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Drivers/RootComplexConfigDxe/RootComple= xConfigDxe.uni +++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/RootComplexConfigDxe/RootComple= xConfigDxe.uni @@ -1,5 +1,5 @@ // -// Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved. +// Copyright (c) 2020 - 2023, Ampere Computing LLC. All rights reserved. // // SPDX-License-Identifier: BSD-2-Clause-Patent // @@ -78,6 +78,7 @@ #string STR_PCIE_RC15_FORM #language en-US "Root Complex 15 C= onfiguration" #string STR_PCIE_RC15_FORM_HELP #language en-US "Root Complex 15 C= onfiguration" =20 +#string STR_PCIE_BIFUR_SELECT_AUTO #language en-US "Auto" #string STR_PCIE_BIFUR_SELECT_VALUE0 #language en-US "x16" #string STR_PCIE_BIFUR_SELECT_VALUE1 #language en-US "x8+x8" #string STR_PCIE_BIFUR_SELECT_VALUE2 #language en-US "x8+x4+x4" --=20 2.39.0