From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mx.groups.io with SMTP id smtpd.web11.102325.1683533854228983101 for ; Mon, 08 May 2023 01:17:38 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=PrRcPNn/; spf=pass (domain: intel.com, ip: 192.55.52.151, mailfrom: zhiguang.liu@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1683533857; x=1715069857; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=opNmylXWH550VB10MCnI3sJ0cXC8IR85JARjGK4++JY=; b=PrRcPNn/3zGKKUGuxVZRVbzwiL2JJdQz3gl2mtKcc3zu8mlt4VZsavpH L2j7qKz2CGtwzRgQqDBs1T4IkDoN70eqTl51N9wWRcQ5H82p0HuKsL5Xd 12oqTgqZR+vJBjJpU1uRb3X8Zfjydd6SxfzCBnvWuldTSztY8el+LQXZl LXWOz9DwGDS07iV2PqvxXduqFZwqUWJC4FKUVBuFGteukk5qChzNj8f+S hrB0+o5z5IBEfgWM2yhdLK+CByf2KJ+Y7CO2cXJ5nn2Wh05l/c/2RTw1c 0NQCjaXJ0EeyvIEbve+xvrebRhugsB0AXN0tL/3OCMZ63gqilc9SXnAas g==; X-IronPort-AV: E=McAfee;i="6600,9927,10703"; a="329948488" X-IronPort-AV: E=Sophos;i="5.99,258,1677571200"; d="scan'208";a="329948488" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 May 2023 01:17:15 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10703"; a="731219087" X-IronPort-AV: E=Sophos;i="5.99,258,1677571200"; d="scan'208";a="731219087" Received: from shwdesfp01.ccr.corp.intel.com ([10.239.158.151]) by orsmga001-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 May 2023 01:17:12 -0700 From: "Zhiguang Liu" To: devel@edk2.groups.io Cc: Zhiguang Liu , Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann , Debkumar De , Catharine West Subject: [PATCH v5 5/5] UefiCpuPkg/ResetVector: Support 5 level page table in ResetVector Date: Mon, 8 May 2023 16:15:04 +0800 Message-Id: <20230508081504.1067-6-zhiguang.liu@intel.com> X-Mailer: git-send-email 2.31.1.windows.1 In-Reply-To: <20230508081504.1067-1-zhiguang.liu@intel.com> References: <20230508081504.1067-1-zhiguang.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add a macro USE_5_LEVEL_PAGE_TABLE to determine whether to create 5 level page table. If macro USE_5_LEVEL_PAGE_TABLE is defined, PML5Table is created at (4G-12K), while PML4Table is at (4G-16K). In runtime check, if 5level paging is supported, use PML5Table, otherwise, use PML4Table. If macro USE_5_LEVEL_PAGE_TABLE is not defined, to save space, 5level paging is not created, and 4level paging is at (4G-12K) and be used. Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann Cc: Debkumar De Cc: Catharine West Signed-off-by: Zhiguang Liu --- .../ResetVector/Vtf0/Ia32/Flat32ToFlat64.asm | 25 +++++++++++++++++-- .../ResetVector/Vtf0/Ia32/PageTables64.asm | 24 ------------------ UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb | 1 - .../ResetVector/Vtf0/X64/PageTables.asm | 9 +++++++ 4 files changed, 32 insertions(+), 27 deletions(-) delete mode 100644 UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm diff --git a/UefiCpuPkg/ResetVector/Vtf0/Ia32/Flat32ToFlat64.asm b/UefiCpuPkg/ResetVector/Vtf0/Ia32/Flat32ToFlat64.asm index 6891397c2a..f119f941a5 100644 --- a/UefiCpuPkg/ResetVector/Vtf0/Ia32/Flat32ToFlat64.asm +++ b/UefiCpuPkg/ResetVector/Vtf0/Ia32/Flat32ToFlat64.asm @@ -2,7 +2,7 @@ ; @file ; Transition from 32 bit flat protected mode into 64 bit flat protected mode ; -; Copyright (c) 2008 - 2018, Intel Corporation. All rights reserved.
+; Copyright (c) 2008 - 2023, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent ; ;------------------------------------------------------------------------------ @@ -14,7 +14,28 @@ BITS 32 ; Transition32FlatTo64Flat: - OneTimeCall SetCr3ForPageTables64 +%ifdef USE_5_LEVEL_PAGE_TABLE + mov eax, 0 + cpuid + cmp eax, 07h ; check if basic CPUID leaf contains leaf 07 + jb NotSupport5LevelPaging ; 5level paging not support, downgrade to 4level paging + mov eax, 07h ; check cpuid leaf 7, subleaf 0 + mov ecx, 0 + cpuid + bt ecx, 16 ; [Bits 16] Supports 5-level paging if 1. + jnc NotSupport5LevelPaging ; 5level paging not support, downgrade to 4level paging + mov eax, ADDR_OF(Pml5) + mov cr3, eax + mov eax, cr4 + bts eax, 12 ; Set LA57=1. + mov cr4, eax + jmp SetCr3Done +NotSupport5LevelPaging: +%endif + + mov eax, ADDR_OF(Pml4) + mov cr3, eax +SetCr3Done: mov eax, cr4 bts eax, 5 ; enable PAE diff --git a/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm b/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm deleted file mode 100644 index f188da20ba..0000000000 --- a/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm +++ /dev/null @@ -1,24 +0,0 @@ -;------------------------------------------------------------------------------ -; @file -; Sets the CR3 register for 64-bit paging -; -; Copyright (c) 2008 - 2023, Intel Corporation. All rights reserved.
-; SPDX-License-Identifier: BSD-2-Clause-Patent -; -;------------------------------------------------------------------------------ - -BITS 32 - -; -; Modified: EAX -; -SetCr3ForPageTables64: - - ; - ; These pages are built into the ROM image in X64/PageTables.asm - ; - mov eax, ADDR_OF(Pml4) - mov cr3, eax - - OneTimeCallRet SetCr3ForPageTables64 - diff --git a/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb b/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb index 136361e62c..5a6563bd34 100644 --- a/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb +++ b/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb @@ -54,7 +54,6 @@ %ifdef ARCH_X64 %include "Ia32/Flat32ToFlat64.asm" -%include "Ia32/PageTables64.asm" %endif %include "Ia16/Real16ToFlat32.asm" diff --git a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm index d66fb62c34..7960b141be 100644 --- a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm +++ b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm @@ -81,4 +81,13 @@ Pml4: ; DQ PAGE_NLE(Pdp) TIMES 0x1000 - ($ - Pml4) DB 0 + +%ifdef USE_5_LEVEL_PAGE_TABLE +Pml5: + ; + ; Pml5 table (only first entry is present, pointing to Pml4) + ; + DQ PAGE_NLE(Pml4) + TIMES 0x1000 - ($ - Pml5) DB 0 +%endif EndOfPageTables: -- 2.31.1.windows.1