From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mx.groups.io with SMTP id smtpd.web11.28255.1683627780311432681 for ; Tue, 09 May 2023 03:23:00 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=mmGpDUsE; spf=pass (domain: intel.com, ip: 134.134.136.24, mailfrom: jiaxin.wu@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1683627780; x=1715163780; h=from:to:subject:date:message-id; bh=VEPm1W/4f2GV/9niX/RVmmOkWchQhrS9S2VUHSq7s2U=; b=mmGpDUsEXaKLS27yvaeSW3ve/vGvjaLmVdeRdQtWe4TY+Qp1HMb+NJUG BbhoxDY2caT9q6xkNpdCGJ7OKN8W5Plbu8aWPgZSqJpDJBZCxlkV6IIUF l53kZQfB/p9MGbktTVpYjdWe57Kav4mETBLfIsvWBr9Ze6AQ7LEsoYsLl hkBkFob98YBS1dIIwY1x/82P6mUThozsHMfZj7ZUYuwTc2TPGjeuBLEoa 8ygklSLMSiThYgeO1pLOjJwiGDUhlvfB41o0Zh1SdbZQfMoNIZCQaHL1m Y9PDwGaUkC5tXp1BwRoC1ZsP1UO/82Kn0fNUWE13VdDLmROju9kvBoNH0 w==; X-IronPort-AV: E=McAfee;i="6600,9927,10704"; a="352058178" X-IronPort-AV: E=Sophos;i="5.99,261,1677571200"; d="scan'208";a="352058178" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 May 2023 03:22:59 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10704"; a="768453988" X-IronPort-AV: E=Sophos;i="5.99,261,1677571200"; d="scan'208";a="768453988" Received: from sh1gapp1009.ccr.corp.intel.com ([10.239.189.219]) by fmsmga004.fm.intel.com with ESMTP; 09 May 2023 03:22:58 -0700 From: "Wu, Jiaxin" To: devel@edk2.groups.io Subject: [PATCH v1 0/3] Target to enable paging from temporary RAM Done Date: Tue, 9 May 2023 18:22:50 +0800 Message-Id: <20230509102253.16632-1-jiaxin.wu@intel.com> X-Mailer: git-send-email 2.16.2.windows.1 For arch X64, system will enable the page table in SPI to cover 0-512G range via CR4.PAE & MSR.LME & CR0.PG & CR3 setting. Existing code doesn't cover the higher address access above 512G before memory-discovered callback. This series patches provide the solution to enable paging from temporary RAM Done. Jiaxin Wu (3): UefiCpuPkg/SecCore: Migrate page table to permanent memory UefiCpuPkg/CpuMpPei: Enable PAE page table if CR0.PG is not set MdeModulePkg/DxeIpl: Align Page table Level setting with previous level. MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c | 39 ++-- UefiCpuPkg/CpuMpPei/CpuMpPei.h | 1 + UefiCpuPkg/CpuMpPei/CpuMpPei.inf | 1 + UefiCpuPkg/CpuMpPei/CpuPaging.c | 228 ++++++++++------------- UefiCpuPkg/SecCore/SecCore.inf | 1 + UefiCpuPkg/SecCore/SecCoreNative.inf | 1 + UefiCpuPkg/SecCore/SecMain.c | 164 ++++++++++++++++ UefiCpuPkg/SecCore/SecMain.h | 4 + 8 files changed, 299 insertions(+), 140 deletions(-) -- 2.16.2.windows.1