From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mx.groups.io with SMTP id smtpd.web11.28255.1683627780311432681 for ; Tue, 09 May 2023 03:23:07 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=llEvgji8; spf=pass (domain: intel.com, ip: 134.134.136.24, mailfrom: jiaxin.wu@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1683627787; x=1715163787; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=8tzDfcxrRGmEGNPrdJu6VnApAnuAAgR1nMQ0er08afM=; b=llEvgji8/EyExN/RWRQMVa1hhKIhni0zw1/KD+q9wxHgQjhLmWNglLVm YMiisClAFgPen4FmKeaUd4I29ZzvKOCezYJX4zzQAfTA5QwSIrBGiuIgT ee3BR/CSfZwadBaR+bkGs7PJYbrRbrLNhoT8ps/T3Oga42R69Hs6FVzu5 wT9fr6KHDuqV9NKlDhAzwuYKIunQfdSUNBdTDElSvVo8rh6Z2yZ397Lq7 Q9rjxQv46HtGNfdnw8WmUwK0n5XFrqMSmaiMLl3iM7NK4Hsxh7+mg3ZdC 3tmXo4Cu6GegTi4e8mF9cp25qYbaKf+f9ejEAgohk8uOr7k0S/DgsLbE5 A==; X-IronPort-AV: E=McAfee;i="6600,9927,10704"; a="352058228" X-IronPort-AV: E=Sophos;i="5.99,261,1677571200"; d="scan'208";a="352058228" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 May 2023 03:23:05 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10704"; a="768454187" X-IronPort-AV: E=Sophos;i="5.99,261,1677571200"; d="scan'208";a="768454187" Received: from sh1gapp1009.ccr.corp.intel.com ([10.239.189.219]) by fmsmga004.fm.intel.com with ESMTP; 09 May 2023 03:23:03 -0700 From: "Wu, Jiaxin" To: devel@edk2.groups.io Cc: Dandan Bi , Liming Gao , Eric Dong , Ray Ni , Zeng Star , Gerd Hoffmann , Rahul Kumar Subject: [PATCH v1 3/3] MdeModulePkg/DxeIpl: Align Page table Level setting with previous level. Date: Tue, 9 May 2023 18:22:53 +0800 Message-Id: <20230509102253.16632-4-jiaxin.wu@intel.com> X-Mailer: git-send-email 2.16.2.windows.1 In-Reply-To: <20230509102253.16632-1-jiaxin.wu@intel.com> References: <20230509102253.16632-1-jiaxin.wu@intel.com> System paging 5 level enabled or not can be checked via CR4.LA57, system preferred Page table Level (PcdUse5LevelPageTable) must align with previous level for X64 mode. This patch is to do the wise check: If X64, Page table Level setting in PcdUse5LevelPageTable must align with previous level. If IA32, Page table Level is decided by PcdUse5LevelPageTable and feature capability. Change-Id: Ia7f7e365c7354cc49f971209bfcbc5af5aded062 Cc: Dandan Bi Cc: Liming Gao Cc: Eric Dong Cc: Ray Ni Cc: Zeng Star Cc: Gerd Hoffmann Cc: Rahul Kumar Signed-off-by: Jiaxin Wu --- MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c | 39 ++++++++++++++++-------- 1 file changed, 27 insertions(+), 12 deletions(-) diff --git a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c index 18b121d768..301e200cd8 100644 --- a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c +++ b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c @@ -737,22 +737,37 @@ CreateIdentityMappingPageTables ( } else { PhysicalAddressBits = 36; } } - Page5LevelSupport = FALSE; - if (PcdGetBool (PcdUse5LevelPageTable)) { - AsmCpuidEx ( - CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, - CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO, - NULL, - NULL, - &EcxFlags.Uint32, - NULL - ); - if (EcxFlags.Bits.FiveLevelPage != 0) { - Page5LevelSupport = TRUE; + // + // Check run in X64 or IA32 + // + if (sizeof (UINTN) == sizeof (UINT64)) { + // + // If X64, Page table Level must align with previous level. + // + Cr4.UintN = AsmReadCr4 (); + Page5LevelSupport = Cr4.Bits.LA57 ? TRUE : FALSE; + ASSERT (PcdGetBool (PcdUse5LevelPageTable) == Page5LevelSupport); + } else { + // + // If IA32, Page table Level is decided by PCD and feature capbility. + // + Page5LevelSupport = FALSE; + if (PcdGetBool (PcdUse5LevelPageTable)) { + AsmCpuidEx ( + CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, + CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO, + NULL, + NULL, + &EcxFlags.Uint32, + NULL + ); + if (EcxFlags.Bits.FiveLevelPage != 0) { + Page5LevelSupport = TRUE; + } } } DEBUG ((DEBUG_INFO, "AddressBits=%u 5LevelPaging=%u 1GPage=%u\n", PhysicalAddressBits, Page5LevelSupport, Page1GSupport)); -- 2.16.2.windows.1