From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mx.groups.io with SMTP id smtpd.web10.16549.1683864953043729668 for ; Thu, 11 May 2023 21:15:53 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=h+p9RoMb; spf=pass (domain: intel.com, ip: 192.55.52.93, mailfrom: jiaxin.wu@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1683864952; x=1715400952; h=from:to:subject:date:message-id; bh=DXZ7mCFfwVrwS2U5q1vt+af9p1NRgzZOSjJb+rS5bYg=; b=h+p9RoMbR71zEgmU3EJ3g2a+QPVile6Ia1zvjWJ7PY9NESzw84DaKKiJ NqUnspnCmp6jQnA/8wqNJuXzBPi3+6ZJikpNlOTN9BBtpZHJPISIWP6p6 Rhq3sF0WUCrWax9AUJT2gMB4MwYLddqyFLZi2+kYPdx9KdyY/z6ygCf32 WWVnzCNkW6aRrf/WCpyztkVR72brzfBo1Pg0TenD+oTVoPaIVVBK5dTtd Oni9doN8D3uoGXBPur84v40zG+mFY251p6IkLjiYIYyI66olfXxH1r9r2 m9jlvPyjUhV1TdCOjXguV618xwyTSe58oRWk6YZiDWzrwwSm2SfR27Knv g==; X-IronPort-AV: E=McAfee;i="6600,9927,10707"; a="348193812" X-IronPort-AV: E=Sophos;i="5.99,269,1677571200"; d="scan'208";a="348193812" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 May 2023 21:15:52 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10707"; a="730658289" X-IronPort-AV: E=Sophos;i="5.99,269,1677571200"; d="scan'208";a="730658289" Received: from sh1gapp1009.ccr.corp.intel.com ([10.239.189.219]) by orsmga008.jf.intel.com with ESMTP; 11 May 2023 21:15:51 -0700 From: "Wu, Jiaxin" To: devel@edk2.groups.io Subject: [PATCH v2 0/5] Target to enable paging from temporary RAM Done Date: Fri, 12 May 2023 12:15:43 +0800 Message-Id: <20230512041548.6416-1-jiaxin.wu@intel.com> X-Mailer: git-send-email 2.16.2.windows.1 For arch X64, system will enable the page table in SPI to cover 0-512G range via CR4.PAE & MSR.LME & CR0.PG & CR3 setting. Existing code doesn't cover the higher address access above 512G before memory-discovered callback. This series patches provide the solution to enable paging from temporary RAM Done. Jiaxin Wu (5): UefiCpuPkg/SecCore: Migrate page table to permanent memory UefiCpuPkg/CpuMpPei: Enable PAE page table if CR0.PG is not set MdeModulePkg/DxeIpl: Align Page table Level setting with previous level. OvmfPkg: Add CpuPageTableLib required by SecCore & CpuMpPei UefiPayloadPkg: Add CpuPageTableLib required by SecCore & CpuMpPei MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c | 39 ++-- OvmfPkg/AmdSev/AmdSevX64.dsc | 2 +- OvmfPkg/CloudHv/CloudHvX64.dsc | 2 +- OvmfPkg/IntelTdx/IntelTdxX64.dsc | 3 +- OvmfPkg/Microvm/MicrovmX64.dsc | 2 +- OvmfPkg/OvmfPkgIa32.dsc | 1 + OvmfPkg/OvmfPkgIa32X64.dsc | 2 +- OvmfPkg/OvmfPkgX64.dsc | 3 +- OvmfPkg/OvmfXen.dsc | 2 +- UefiCpuPkg/CpuMpPei/CpuMpPei.h | 1 + UefiCpuPkg/CpuMpPei/CpuMpPei.inf | 1 + UefiCpuPkg/CpuMpPei/CpuPaging.c | 215 +++++++++-------------- UefiCpuPkg/SecCore/SecCore.inf | 1 + UefiCpuPkg/SecCore/SecCoreNative.inf | 1 + UefiCpuPkg/SecCore/SecMain.c | 152 ++++++++++++++++ UefiCpuPkg/SecCore/SecMain.h | 4 + UefiPayloadPkg/UefiPayloadPkg.dsc | 2 +- 17 files changed, 282 insertions(+), 151 deletions(-) -- 2.16.2.windows.1