From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mx.groups.io with SMTP id smtpd.web10.16549.1683864953043729668 for ; Thu, 11 May 2023 21:15:54 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=Cf8ZFyu1; spf=pass (domain: intel.com, ip: 192.55.52.93, mailfrom: jiaxin.wu@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1683864954; x=1715400954; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=YTbJ1EwXp210b42Aq6p2yqwrD+VFtc8gkvaELfrdQV4=; b=Cf8ZFyu1uouduqP3GZII6aPH9iwKoCu1/cBthrJ+d5VuckWl+Hgg/znB M1webCJSZxB+zYZEtChAPJ1+04QTdoUVdBkufpKg+InR3opRQ/7IPLKo/ lZi1EH7gupNadn8tNN6TsXgG5+nOaBFXnWOPZsUl2T+buZb6WJg0cgBdt mfJmGXD+nZH/cRjSTKH52afdrc/P6Fv/a3FvxUu5nGbEr8WsgELuw9GXU UO/XSv2LH3/Tu0sSWCUVY6NZgKX+Inz68PUV38zi3Yqg53eLfzG16Ovgd T9BGEGLaBDXbrR+OHjKhK/4UJhKVUGRNRManqqLhhzaM443sGrDriEIL1 w==; X-IronPort-AV: E=McAfee;i="6600,9927,10707"; a="348193828" X-IronPort-AV: E=Sophos;i="5.99,269,1677571200"; d="scan'208";a="348193828" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 May 2023 21:15:54 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10707"; a="730658295" X-IronPort-AV: E=Sophos;i="5.99,269,1677571200"; d="scan'208";a="730658295" Received: from sh1gapp1009.ccr.corp.intel.com ([10.239.189.219]) by orsmga008.jf.intel.com with ESMTP; 11 May 2023 21:15:52 -0700 From: "Wu, Jiaxin" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Zeng Star , Gerd Hoffmann , Rahul Kumar Subject: [PATCH v2 1/5] UefiCpuPkg/SecCore: Migrate page table to permanent memory Date: Fri, 12 May 2023 12:15:44 +0800 Message-Id: <20230512041548.6416-2-jiaxin.wu@intel.com> X-Mailer: git-send-email 2.16.2.windows.1 In-Reply-To: <20230512041548.6416-1-jiaxin.wu@intel.com> References: <20230512041548.6416-1-jiaxin.wu@intel.com> Background: For arch X64, system will enable the page table in SPI to cover 0-512G range via CR4.PAE & MSR.LME & CR0.PG & CR3 setting (see ResetVector code). Existing code doesn't cover the higher address access above 512G before memory-discovered callback. That will be potential problem if system access the higher address after the transition from temporary RAM to permanent MEM RAM. Solution: This patch is to migrate page table to permanent memory to map entire physical address space if CR0.PG is set during temporary RAM Done. Cc: Eric Dong Cc: Ray Ni Cc: Zeng Star Cc: Gerd Hoffmann Cc: Rahul Kumar Signed-off-by: Jiaxin Wu --- UefiCpuPkg/SecCore/SecCore.inf | 1 + UefiCpuPkg/SecCore/SecCoreNative.inf | 1 + UefiCpuPkg/SecCore/SecMain.c | 152 +++++++++++++++++++++++++++++++++++ UefiCpuPkg/SecCore/SecMain.h | 4 + 4 files changed, 158 insertions(+) diff --git a/UefiCpuPkg/SecCore/SecCore.inf b/UefiCpuPkg/SecCore/SecCore.inf index 3758aded3b..cab69b8b97 100644 --- a/UefiCpuPkg/SecCore/SecCore.inf +++ b/UefiCpuPkg/SecCore/SecCore.inf @@ -53,10 +53,11 @@ CpuExceptionHandlerLib ReportStatusCodeLib PeiServicesLib PeiServicesTablePointerLib HobLib + CpuPageTableLib [Ppis] ## SOMETIMES_CONSUMES ## PRODUCES gEfiSecPlatformInformationPpiGuid diff --git a/UefiCpuPkg/SecCore/SecCoreNative.inf b/UefiCpuPkg/SecCore/SecCoreNative.inf index 1ee6ff7d88..fa241cca94 100644 --- a/UefiCpuPkg/SecCore/SecCoreNative.inf +++ b/UefiCpuPkg/SecCore/SecCoreNative.inf @@ -50,10 +50,11 @@ CpuExceptionHandlerLib ReportStatusCodeLib PeiServicesLib PeiServicesTablePointerLib HobLib + CpuPageTableLib [Ppis] ## SOMETIMES_CONSUMES ## PRODUCES gEfiSecPlatformInformationPpiGuid diff --git a/UefiCpuPkg/SecCore/SecMain.c b/UefiCpuPkg/SecCore/SecMain.c index 95375850ec..8ec0b654fb 100644 --- a/UefiCpuPkg/SecCore/SecMain.c +++ b/UefiCpuPkg/SecCore/SecMain.c @@ -70,10 +70,139 @@ MigrateGdt ( AsmWriteGdtr (&Gdtr); return EFI_SUCCESS; } +/** + Migrate page table to permanent memory mapping entire physical address space. + + @retval EFI_SUCCESS The PageTable was migrated successfully. + @retval EFI_UNSUPPORTED Unsupport to migrate page table to permanent memory if IA-32e Mode not actived. + @retval EFI_OUT_OF_RESOURCES The PageTable could not be migrated due to lack of available memory. + +**/ +EFI_STATUS +MigratePageTable ( + VOID + ) +{ + EFI_STATUS Status; + IA32_CR4 Cr4; + BOOLEAN Page5LevelSupport; + UINT32 RegEax; + CPUID_EXTENDED_CPU_SIG_EDX RegEdx; + BOOLEAN Page1GSupport; + PAGING_MODE PagingMode; + CPUID_VIR_PHY_ADDRESS_SIZE_EAX VirPhyAddressSize; + UINT32 MaxExtendedFunctionId; + UINTN PageTable; + EFI_PHYSICAL_ADDRESS Buffer; + UINTN BufferSize; + IA32_MAP_ATTRIBUTE MapAttribute; + IA32_MAP_ATTRIBUTE MapMask; + + VirPhyAddressSize.Uint32 = 0; + PageTable = 0; + BufferSize = 0; + MapAttribute.Uint64 = 0; + MapMask.Uint64 = MAX_UINT64; + MapAttribute.Bits.Present = 1; + MapAttribute.Bits.ReadWrite = 1; + + // + // Check Page5Level Support or not. + // + Cr4.UintN = AsmReadCr4 (); + Page5LevelSupport = (Cr4.Bits.LA57 ? TRUE : FALSE); + + // + // Check Page1G Support or not. + // + Page1GSupport = FALSE; + AsmCpuid (CPUID_EXTENDED_FUNCTION, &RegEax, NULL, NULL, NULL); + if (RegEax >= CPUID_EXTENDED_CPU_SIG) { + AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, NULL, &(RegEdx.Uint32)); + if ((RegEdx.Bits.Page1GB) != 0) { + Page1GSupport = TRUE; + } + } + + // + // Decide Paging Mode according Page5LevelSupport & Page1GSupport. + // + if (Page5LevelSupport) { + PagingMode = Page1GSupport ? Paging5Level1GB : Paging5Level; + } else { + PagingMode = Page1GSupport ? Paging4Level1GB : Paging4Level; + } + + // + // Get Maximum Physical Address Bits + // Get the number of address lines; Maximum Physical Address is 2^PhysicalAddressBits - 1. + // If CPUID does not supported, then use a max value of 36 as per SDM 3A, 4.1.4. + // + AsmCpuid (CPUID_EXTENDED_FUNCTION, &MaxExtendedFunctionId, NULL, NULL, NULL); + if (MaxExtendedFunctionId >= CPUID_VIR_PHY_ADDRESS_SIZE) { + AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, &VirPhyAddressSize.Uint32, NULL, NULL, NULL); + } else { + VirPhyAddressSize.Bits.PhysicalAddressBits = 36; + } + + if ((PagingMode == Paging4Level1GB) || (PagingMode == Paging4Level)) { + // + // The max lineaddress bits is 48 for 4 level page table. + // + VirPhyAddressSize.Bits.PhysicalAddressBits = MIN (VirPhyAddressSize.Bits.PhysicalAddressBits, 48); + } + + // + // Get required buffer size for the pagetable that will be created. + // + Status = PageTableMap (&PageTable, PagingMode, 0, &BufferSize, 0, LShiftU64 (1, VirPhyAddressSize.Bits.PhysicalAddressBits), &MapAttribute, &MapMask, NULL); + ASSERT (Status == EFI_BUFFER_TOO_SMALL); + if (Status != EFI_BUFFER_TOO_SMALL) { + return Status; + } + + // + // Allocate required Buffer. + // + Status = PeiServicesAllocatePages ( + EfiBootServicesData, + EFI_SIZE_TO_PAGES (BufferSize), + &Buffer + ); + if (EFI_ERROR (Status)) { + return EFI_OUT_OF_RESOURCES; + } + + // + // Create PageTable in permanent memory. + // + Status = PageTableMap (&PageTable, PagingMode, (VOID *)(UINTN)Buffer, &BufferSize, 0, LShiftU64 (1, VirPhyAddressSize.Bits.PhysicalAddressBits), &MapAttribute, &MapMask, NULL); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR (Status) || (PageTable == 0)) { + return EFI_OUT_OF_RESOURCES; + } + + // + // Write the Pagetable to CR3. + // + AsmWriteCr3 (PageTable); + + DEBUG (( + DEBUG_INFO, + "MigratePageTable: Created PageTable = 0x%lx, BufferSize = %x, PagingMode = 0x%lx, Support Max Physical Address Bits = %d\n", + PageTable, + BufferSize, + (UINTN)PagingMode, + VirPhyAddressSize.Bits.PhysicalAddressBits + )); + + return Status; +} + // // These are IDT entries pointing to 10:FFFFFFE4h. // UINT64 mIdtEntryTemplate = 0xffff8e000010ffe4ULL; @@ -451,10 +580,11 @@ SecTemporaryRamDone ( EFI_STATUS Status2; UINTN Index; BOOLEAN State; EFI_PEI_PPI_DESCRIPTOR *PeiPpiDescriptor; REPUBLISH_SEC_PPI_PPI *RepublishSecPpiPpi; + IA32_CR0 Cr0; // // Republish Sec Platform Information(2) PPI // RepublishSecPlatformInformationPpi (); @@ -492,10 +622,32 @@ SecTemporaryRamDone ( if (PcdGetBool (PcdMigrateTemporaryRamFirmwareVolumes)) { Status = MigrateGdt (); ASSERT_EFI_ERROR (Status); } + // + // Migrate page table to permanent memory mapping entire physical address space if CR0.PG is set. + // + Cr0.UintN = AsmReadCr0 (); + if (Cr0.Bits.PG != 0) { + // + // CR4.PAE must be enabled. + // + ASSERT ((AsmReadCr4 () & BIT5) != 0); + + // + // Assume CPU runs in 64bit mode if paging is enabled. + // + ASSERT (sizeof (UINTN) == sizeof (UINT64)); + + Status = MigratePageTable (); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_WARN, "SecTemporaryRamDone: Failed to migrate page table to permanent memory: %r.\n", Status)); + ASSERT_EFI_ERROR (Status); + } + } + // // Disable Temporary RAM after Stack and Heap have been migrated at this point. // SecPlatformDisableTemporaryMemory (); diff --git a/UefiCpuPkg/SecCore/SecMain.h b/UefiCpuPkg/SecCore/SecMain.h index 880e6cd1b8..b50d96e45b 100644 --- a/UefiCpuPkg/SecCore/SecMain.h +++ b/UefiCpuPkg/SecCore/SecMain.h @@ -17,10 +17,11 @@ #include #include #include +#include #include #include #include #include #include @@ -30,10 +31,13 @@ #include #include #include #include #include +#include +#include +#include #define SEC_IDT_ENTRY_COUNT 34 typedef struct _SEC_IDT_TABLE { // -- 2.16.2.windows.1