From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mx.groups.io with SMTP id smtpd.web10.16549.1683864953043729668 for ; Thu, 11 May 2023 21:15:59 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=ikomxedh; spf=pass (domain: intel.com, ip: 192.55.52.93, mailfrom: jiaxin.wu@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1683864958; x=1715400958; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=tv67e9QYSpPbKzWuE3gtPV3QPGkQs4cCbHzI/uxFicw=; b=ikomxedhr4aW8bVJft9lvHEk/EPffxuqEn6tI/VH7vIxtDFi2qyy/VJf oJUIejGZq7TFfVKCpcfCSElLsU7P8IgO3cjliJddQ4m0C4tdys5AdbowS Dw96ZZfxnm90/gdPhf2z9kafo9QDqwGyQGkdOwUnEvowv0/HsyK7QoLnI uyapzARiZwNzxEbcHQfl+7lEx2A3HEfWgV0bY976F2aiSJRpOPraazAmq mSPVDLURXtOMsi+3hKvQzDWVnRP6hnDTLyJWssZ1Fpk2680jn6FKIW/ha O+6SsTOZPAWkS4qFVz29ZRuKkINjMefTmTug+YnYU8YohalvJNVEdNYTT A==; X-IronPort-AV: E=McAfee;i="6600,9927,10707"; a="348193872" X-IronPort-AV: E=Sophos;i="5.99,269,1677571200"; d="scan'208";a="348193872" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 May 2023 21:15:58 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10707"; a="730658305" X-IronPort-AV: E=Sophos;i="5.99,269,1677571200"; d="scan'208";a="730658305" Received: from sh1gapp1009.ccr.corp.intel.com ([10.239.189.219]) by orsmga008.jf.intel.com with ESMTP; 11 May 2023 21:15:56 -0700 From: "Wu, Jiaxin" To: devel@edk2.groups.io Cc: Dandan Bi , Liming Gao , Eric Dong , Ray Ni , Zeng Star , Gerd Hoffmann , Rahul Kumar Subject: [PATCH v2 3/5] MdeModulePkg/DxeIpl: Align Page table Level setting with previous level. Date: Fri, 12 May 2023 12:15:46 +0800 Message-Id: <20230512041548.6416-4-jiaxin.wu@intel.com> X-Mailer: git-send-email 2.16.2.windows.1 In-Reply-To: <20230512041548.6416-1-jiaxin.wu@intel.com> References: <20230512041548.6416-1-jiaxin.wu@intel.com> System paging 5 level enabled or not can be checked via CR4.LA57, system preferred Page table Level (PcdUse5LevelPageTable) must align with previous level for 64bit long mode. This patch is to do the wise check: If cpu has already runned in 64bit long mode PEI, Page table Level in DXE must align with previous level. If cpu runs in 32bit protected mode PEI, Page table Level in DXE is decided by PCD and feature capability. Cc: Dandan Bi Cc: Liming Gao Cc: Eric Dong Cc: Ray Ni Cc: Zeng Star Cc: Gerd Hoffmann Cc: Rahul Kumar Signed-off-by: Jiaxin Wu --- MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c | 39 ++++++++++++++++-------- 1 file changed, 27 insertions(+), 12 deletions(-) diff --git a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c index 18b121d768..a8e46eacc3 100644 --- a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c +++ b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c @@ -737,22 +737,37 @@ CreateIdentityMappingPageTables ( } else { PhysicalAddressBits = 36; } } - Page5LevelSupport = FALSE; - if (PcdGetBool (PcdUse5LevelPageTable)) { - AsmCpuidEx ( - CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, - CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO, - NULL, - NULL, - &EcxFlags.Uint32, - NULL - ); - if (EcxFlags.Bits.FiveLevelPage != 0) { - Page5LevelSupport = TRUE; + // + // Check cpu runs in 64bit long mode or 32bit protected mode. + // + if (sizeof (UINTN) == sizeof (UINT64)) { + // + // If cpu has already runned in 64bit long mode PEI, Page table Level in DXE must align with previous level. + // + Cr4.UintN = AsmReadCr4 (); + Page5LevelSupport = Cr4.Bits.LA57 ? TRUE : FALSE; + ASSERT (PcdGetBool (PcdUse5LevelPageTable) == Page5LevelSupport); + } else { + // + // If cpu runs in 32bit protected mode PEI, Page table Level in DXE is decided by PCD and feature capability. + // + Page5LevelSupport = FALSE; + if (PcdGetBool (PcdUse5LevelPageTable)) { + AsmCpuidEx ( + CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, + CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO, + NULL, + NULL, + &EcxFlags.Uint32, + NULL + ); + if (EcxFlags.Bits.FiveLevelPage != 0) { + Page5LevelSupport = TRUE; + } } } DEBUG ((DEBUG_INFO, "AddressBits=%u 5LevelPaging=%u 1GPage=%u\n", PhysicalAddressBits, Page5LevelSupport, Page1GSupport)); -- 2.16.2.windows.1