* [PATCH v6 1/5] UefiCpuPkg/ResetVector: Rename macros about page table.
2023-05-15 1:41 [PATCH v6 0/5] UefiCpuPkg/ResetVector: Refine page table creation, and support 5 Level paging Zhiguang Liu
@ 2023-05-15 1:41 ` Zhiguang Liu
2023-05-15 1:41 ` [PATCH v6 2/5] UefiCpuPkg/ResetVector: Simplify page table creation in ResetVector Zhiguang Liu
` (4 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Zhiguang Liu @ 2023-05-15 1:41 UTC (permalink / raw)
To: devel
Cc: Liu, Zhiguang, Eric Dong, Ray Ni, Rahul Kumar, Gerd Hoffmann,
Debkumar De, Catharine West, Zhiguang Liu
From: "Liu, Zhiguang" <Zhiguang.Liu@intel.com>
This patch only renames macro, with no code logic impacted.
Two purpose to rename macro:
1. Align some macro name in PageTables1G.asm and PageTables2M.asm, so
that these two files can be easily combined later.
2. Some Macro names such as PDP are not accurate, since 4 level page
entry also uses this macro. PAGE_NLE (no leaf entry) is better
Cc: Eric Dong <eric.dong@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Tested-by: Gerd Hoffmann <kraxel@redhat.com>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Cc: Debkumar De <debkumar.de@intel.com>
Cc: Catharine West <catharine.west@intel.com>
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
---
.../ResetVector/Vtf0/X64/PageTables1G.asm | 26 +++++++++-----
.../ResetVector/Vtf0/X64/PageTables2M.asm | 35 +++++++++++--------
2 files changed, 39 insertions(+), 22 deletions(-)
diff --git a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables1G.asm b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables1G.asm
index 19bd3d5a92..20a61f949c 100644
--- a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables1G.asm
+++ b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables1G.asm
@@ -2,7 +2,7 @@
; @file
; Emits Page Tables for 1:1 mapping of the addresses 0 - 0x8000000000 (512GB)
;
-; Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+; Copyright (c) 2021 - 2023, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent
; Linear-Address Translation to a 1-GByte Page
;
@@ -12,11 +12,18 @@ BITS 64
%define ALIGN_TOP_TO_4K_FOR_PAGING
-%define PAGE_PDP_ATTR (PAGE_ACCESSED + \
+;
+; Page table non-leaf entry attribute
+;
+%define PAGE_NLE_ATTR (PAGE_ACCESSED + \
PAGE_READ_WRITE + \
PAGE_PRESENT)
-%define PAGE_PDP_1G_ATTR (PAGE_ACCESSED + \
+;
+; Page table big leaf entry attribute:
+; PDPTE 1GB entry or PDE 2MB entry
+;
+%define PAGE_BLE_ATTR (PAGE_ACCESSED + \
PAGE_READ_WRITE + \
PAGE_DIRTY + \
PAGE_PRESENT + \
@@ -25,10 +32,13 @@ BITS 64
%define PGTBLS_OFFSET(x) ((x) - TopLevelPageDirectory)
%define PGTBLS_ADDR(x) (ADDR_OF(TopLevelPageDirectory) + (x))
-%define PDP(offset) (ADDR_OF(TopLevelPageDirectory) + (offset) + \
- PAGE_PDP_ATTR)
+;
+; Page table non-leaf entry
+;
+%define PAGE_NLE(offset) (ADDR_OF(TopLevelPageDirectory) + (offset) + \
+ PAGE_NLE_ATTR)
-%define PDP_1G(x) ((x << 30) + PAGE_PDP_1G_ATTR)
+%define PAGE_PDPTE_1GB(x) ((x << 30) + PAGE_BLE_ATTR)
ALIGN 16
@@ -37,7 +47,7 @@ TopLevelPageDirectory:
;
; Top level Page Directory Pointers (1 * 512GB entry)
;
- DQ PDP(0x1000)
+ DQ PAGE_NLE(0x1000)
TIMES 0x1000-PGTBLS_OFFSET($) DB 0
;
@@ -45,7 +55,7 @@ TopLevelPageDirectory:
;
%assign i 0
%rep 512
- DQ PDP_1G(i)
+ DQ PAGE_PDPTE_1GB(i)
%assign i i+1
%endrep
TIMES 0x2000-PGTBLS_OFFSET($) DB 0
diff --git a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables2M.asm b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables2M.asm
index b97df384ac..1221b023fe 100644
--- a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables2M.asm
+++ b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables2M.asm
@@ -2,7 +2,7 @@
; @file
; Emits Page Tables for 1:1 mapping of the addresses 0 - 0x100000000 (4GB)
;
-; Copyright (c) 2008 - 2014, Intel Corporation. All rights reserved.<BR>
+; Copyright (c) 2008 - 2023, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
;------------------------------------------------------------------------------
@@ -11,29 +11,36 @@ BITS 64
%define ALIGN_TOP_TO_4K_FOR_PAGING
-%define PAGE_2M_PDE_ATTR (PAGE_SIZE + \
+;
+; Page table big leaf entry attribute:
+; PDPTE 1GB entry or PDE 2MB entry
+;
+%define PAGE_BLE_ATTR (PAGE_SIZE + \
PAGE_ACCESSED + \
PAGE_DIRTY + \
PAGE_READ_WRITE + \
PAGE_PRESENT)
-%define PAGE_PDP_ATTR (PAGE_ACCESSED + \
- PAGE_READ_WRITE + \
- PAGE_PRESENT)
+;
+; Page table non-leaf entry attribute
+;
+%define PAGE_NLE_ATTR (PAGE_ACCESSED + \
+ PAGE_READ_WRITE + \
+ PAGE_PRESENT)
%define PGTBLS_OFFSET(x) ((x) - TopLevelPageDirectory)
%define PGTBLS_ADDR(x) (ADDR_OF(TopLevelPageDirectory) + (x))
-%define PDP(offset) (ADDR_OF(TopLevelPageDirectory) + (offset) + \
- PAGE_PDP_ATTR)
-%define PTE_2MB(x) ((x << 21) + PAGE_2M_PDE_ATTR)
+%define PAGE_NLE(offset) (ADDR_OF(TopLevelPageDirectory) + (offset) + \
+ PAGE_NLE_ATTR)
+%define PAGE_PDE_2MB(x) ((x << 21) + PAGE_BLE_ATTR)
TopLevelPageDirectory:
;
; Top level Page Directory Pointers (1 * 512GB entry)
;
- DQ PDP(0x1000)
+ DQ PAGE_NLE(0x1000)
;
@@ -41,10 +48,10 @@ TopLevelPageDirectory:
;
TIMES 0x1000-PGTBLS_OFFSET($) DB 0
- DQ PDP(0x2000)
- DQ PDP(0x3000)
- DQ PDP(0x4000)
- DQ PDP(0x5000)
+ DQ PAGE_NLE(0x2000)
+ DQ PAGE_NLE(0x3000)
+ DQ PAGE_NLE(0x4000)
+ DQ PAGE_NLE(0x5000)
;
; Page Table Entries (2048 * 2MB entries => 4GB)
@@ -53,7 +60,7 @@ TopLevelPageDirectory:
%assign i 0
%rep 0x800
- DQ PTE_2MB(i)
+ DQ PAGE_PDE_2MB(i)
%assign i i+1
%endrep
--
2.31.1.windows.1
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH v6 2/5] UefiCpuPkg/ResetVector: Simplify page table creation in ResetVector
2023-05-15 1:41 [PATCH v6 0/5] UefiCpuPkg/ResetVector: Refine page table creation, and support 5 Level paging Zhiguang Liu
2023-05-15 1:41 ` [PATCH v6 1/5] UefiCpuPkg/ResetVector: Rename macros about page table Zhiguang Liu
@ 2023-05-15 1:41 ` Zhiguang Liu
2023-05-15 1:41 ` [PATCH v6 3/5] UefiCpuPkg/ResetVector: Combine PageTables1G.asm and PageTables2M.asm Zhiguang Liu
` (3 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Zhiguang Liu @ 2023-05-15 1:41 UTC (permalink / raw)
To: devel
Cc: Liu, Zhiguang, Eric Dong, Ray Ni, Rahul Kumar, Gerd Hoffmann,
Debkumar De, Catharine West, Zhiguang Liu
From: "Liu, Zhiguang" <Zhiguang.Liu@intel.com>
Currently, page table creation has many hard-code values about the
offset to the start of page table. To simplify it, add Labels such
as Pml4, Pdp and Pd, so that we can remove many hard-code values
Cc: Eric Dong <eric.dong@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Tested-by: Gerd Hoffmann <kraxel@redhat.com>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Cc: Debkumar De <debkumar.de@intel.com>
Cc: Catharine West <catharine.west@intel.com>
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
---
.../ResetVector/Vtf0/Ia32/PageTables64.asm | 4 +--
.../ResetVector/Vtf0/X64/PageTables1G.asm | 18 ++++------
.../ResetVector/Vtf0/X64/PageTables2M.asm | 34 ++++++++-----------
3 files changed, 24 insertions(+), 32 deletions(-)
diff --git a/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm b/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm
index 87a4125d4b..f188da20ba 100644
--- a/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm
+++ b/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm
@@ -2,7 +2,7 @@
; @file
; Sets the CR3 register for 64-bit paging
;
-; Copyright (c) 2008 - 2013, Intel Corporation. All rights reserved.<BR>
+; Copyright (c) 2008 - 2023, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
;------------------------------------------------------------------------------
@@ -17,7 +17,7 @@ SetCr3ForPageTables64:
;
; These pages are built into the ROM image in X64/PageTables.asm
;
- mov eax, ADDR_OF(TopLevelPageDirectory)
+ mov eax, ADDR_OF(Pml4)
mov cr3, eax
OneTimeCallRet SetCr3ForPageTables64
diff --git a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables1G.asm b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables1G.asm
index 20a61f949c..f5b8da0015 100644
--- a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables1G.asm
+++ b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables1G.asm
@@ -29,35 +29,31 @@ BITS 64
PAGE_PRESENT + \
PAGE_SIZE)
-%define PGTBLS_OFFSET(x) ((x) - TopLevelPageDirectory)
-%define PGTBLS_ADDR(x) (ADDR_OF(TopLevelPageDirectory) + (x))
-
;
; Page table non-leaf entry
;
-%define PAGE_NLE(offset) (ADDR_OF(TopLevelPageDirectory) + (offset) + \
+%define PAGE_NLE(address) (ADDR_OF(address) + \
PAGE_NLE_ATTR)
%define PAGE_PDPTE_1GB(x) ((x << 30) + PAGE_BLE_ATTR)
ALIGN 16
-TopLevelPageDirectory:
-
+Pml4:
;
- ; Top level Page Directory Pointers (1 * 512GB entry)
+ ; PML4 (1 * 512GB entry)
;
- DQ PAGE_NLE(0x1000)
+ DQ PAGE_NLE(Pdp)
+ TIMES 0x1000 - ($ - Pml4) DB 0
- TIMES 0x1000-PGTBLS_OFFSET($) DB 0
+Pdp:
;
- ; Next level Page Directory Pointers (512 * 1GB entries => 512GB)
+ ; Page-directory pointer table (512 * 1GB entries => 512GB)
;
%assign i 0
%rep 512
DQ PAGE_PDPTE_1GB(i)
%assign i i+1
%endrep
- TIMES 0x2000-PGTBLS_OFFSET($) DB 0
EndOfPageTables:
diff --git a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables2M.asm b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables2M.asm
index 1221b023fe..731dabad4d 100644
--- a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables2M.asm
+++ b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables2M.asm
@@ -28,36 +28,32 @@ BITS 64
PAGE_READ_WRITE + \
PAGE_PRESENT)
-%define PGTBLS_OFFSET(x) ((x) - TopLevelPageDirectory)
-%define PGTBLS_ADDR(x) (ADDR_OF(TopLevelPageDirectory) + (x))
-
-%define PAGE_NLE(offset) (ADDR_OF(TopLevelPageDirectory) + (offset) + \
+%define PAGE_NLE(address) (ADDR_OF(address) + \
PAGE_NLE_ATTR)
%define PAGE_PDE_2MB(x) ((x << 21) + PAGE_BLE_ATTR)
-TopLevelPageDirectory:
-
+Pml4:
;
- ; Top level Page Directory Pointers (1 * 512GB entry)
+ ; PML4 (1 * 512GB entry)
;
- DQ PAGE_NLE(0x1000)
-
+ DQ PAGE_NLE(Pdp)
+ TIMES 0x1000 - ($ - Pml4) DB 0
+Pdp:
;
- ; Next level Page Directory Pointers (4 * 1GB entries => 4GB)
+ ; Page-directory pointer table (4 * 1GB entries => 4GB)
;
- TIMES 0x1000-PGTBLS_OFFSET($) DB 0
-
- DQ PAGE_NLE(0x2000)
- DQ PAGE_NLE(0x3000)
- DQ PAGE_NLE(0x4000)
- DQ PAGE_NLE(0x5000)
+ DQ PAGE_NLE(Pd)
+ DQ PAGE_NLE(Pd + 0x1000)
+ DQ PAGE_NLE(Pd + 0x2000)
+ DQ PAGE_NLE(Pd + 0x3000)
+ TIMES 0x1000 - ($ - Pdp) DB 0
+Pd:
;
- ; Page Table Entries (2048 * 2MB entries => 4GB)
+ ; Page-Directory (2048 * 2MB entries => 4GB)
+ ; Four pages below, each is pointed by one entry in Pdp.
;
- TIMES 0x2000-PGTBLS_OFFSET($) DB 0
-
%assign i 0
%rep 0x800
DQ PAGE_PDE_2MB(i)
--
2.31.1.windows.1
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH v6 3/5] UefiCpuPkg/ResetVector: Combine PageTables1G.asm and PageTables2M.asm
2023-05-15 1:41 [PATCH v6 0/5] UefiCpuPkg/ResetVector: Refine page table creation, and support 5 Level paging Zhiguang Liu
2023-05-15 1:41 ` [PATCH v6 1/5] UefiCpuPkg/ResetVector: Rename macros about page table Zhiguang Liu
2023-05-15 1:41 ` [PATCH v6 2/5] UefiCpuPkg/ResetVector: Simplify page table creation in ResetVector Zhiguang Liu
@ 2023-05-15 1:41 ` Zhiguang Liu
2023-05-15 1:41 ` [PATCH v6 4/5] UefiCpuPkg/ResetVector: Modify Page Table in ResetVector Zhiguang Liu
` (2 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Zhiguang Liu @ 2023-05-15 1:41 UTC (permalink / raw)
To: devel
Cc: Liu, Zhiguang, Eric Dong, Ray Ni, Rahul Kumar, Gerd Hoffmann,
Debkumar De, Catharine West, Zhiguang Liu
From: "Liu, Zhiguang" <Zhiguang.Liu@intel.com>
Combine PageTables1G.asm and PageTables2M.asm to reuse code.
Cc: Eric Dong <eric.dong@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Tested-by: Gerd Hoffmann <kraxel@redhat.com>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Cc: Debkumar De <debkumar.de@intel.com>
Cc: Catharine West <catharine.west@intel.com>
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
---
UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb | 8 +--
.../X64/{PageTables1G.asm => PageTables.asm} | 38 ++++++++---
.../ResetVector/Vtf0/X64/PageTables2M.asm | 63 -------------------
3 files changed, 33 insertions(+), 76 deletions(-)
rename UefiCpuPkg/ResetVector/Vtf0/X64/{PageTables1G.asm => PageTables.asm} (57%)
delete mode 100644 UefiCpuPkg/ResetVector/Vtf0/X64/PageTables2M.asm
diff --git a/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb b/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb
index bdea1fb875..136361e62c 100644
--- a/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb
+++ b/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb
@@ -2,7 +2,7 @@
; @file
; This file includes all other code files to assemble the reset vector code
;
-; Copyright (c) 2008 - 2013, Intel Corporation. All rights reserved.<BR>
+; Copyright (c) 2008 - 2023, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
;------------------------------------------------------------------------------
@@ -38,11 +38,7 @@
%include "PageTables.inc"
%ifdef ARCH_X64
- %ifdef PAGE_TABLE_1G
- %include "X64/PageTables1G.asm"
- %else
- %include "X64/PageTables2M.asm"
- %endif
+ %include "X64/PageTables.asm"
%endif
%ifdef DEBUG_PORT80
diff --git a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables1G.asm b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm
similarity index 57%
rename from UefiCpuPkg/ResetVector/Vtf0/X64/PageTables1G.asm
rename to UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm
index f5b8da0015..9b492b063f 100644
--- a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables1G.asm
+++ b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm
@@ -1,10 +1,11 @@
;------------------------------------------------------------------------------
; @file
-; Emits Page Tables for 1:1 mapping of the addresses 0 - 0x8000000000 (512GB)
+; Emits Page Tables for 1:1 mapping.
+; If using 1G page table, map addresses 0 - 0x8000000000 (512GB),
+; else, map addresses 0 - 0x100000000 (4GB)
;
; Copyright (c) 2021 - 2023, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent
-; Linear-Address Translation to a 1-GByte Page
;
;------------------------------------------------------------------------------
@@ -36,6 +37,7 @@ BITS 64
PAGE_NLE_ATTR)
%define PAGE_PDPTE_1GB(x) ((x << 30) + PAGE_BLE_ATTR)
+%define PAGE_PDE_2MB(x) ((x << 21) + PAGE_BLE_ATTR)
ALIGN 16
@@ -46,14 +48,36 @@ Pml4:
DQ PAGE_NLE(Pdp)
TIMES 0x1000 - ($ - Pml4) DB 0
+%ifdef PAGE_TABLE_1G
Pdp:
;
; Page-directory pointer table (512 * 1GB entries => 512GB)
;
-%assign i 0
-%rep 512
- DQ PAGE_PDPTE_1GB(i)
- %assign i i+1
-%endrep
+ %assign i 0
+ %rep 512
+ DQ PAGE_PDPTE_1GB(i)
+ %assign i i+1
+ %endrep
+%else
+Pdp:
+ ;
+ ; Page-directory pointer table (4 * 1GB entries => 4GB)
+ ;
+ DQ PAGE_NLE(Pd)
+ DQ PAGE_NLE(Pd + 0x1000)
+ DQ PAGE_NLE(Pd + 0x2000)
+ DQ PAGE_NLE(Pd + 0x3000)
+ TIMES 0x1000 - ($ - Pdp) DB 0
+Pd:
+ ;
+ ; Page-Directory (2048 * 2MB entries => 4GB)
+ ; Four pages below, each is pointed by one entry in Pdp.
+ ;
+ %assign i 0
+ %rep 0x800
+ DQ PAGE_PDE_2MB(i)
+ %assign i i+1
+ %endrep
+%endif
EndOfPageTables:
diff --git a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables2M.asm b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables2M.asm
deleted file mode 100644
index 731dabad4d..0000000000
--- a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables2M.asm
+++ /dev/null
@@ -1,63 +0,0 @@
-;------------------------------------------------------------------------------
-; @file
-; Emits Page Tables for 1:1 mapping of the addresses 0 - 0x100000000 (4GB)
-;
-; Copyright (c) 2008 - 2023, Intel Corporation. All rights reserved.<BR>
-; SPDX-License-Identifier: BSD-2-Clause-Patent
-;
-;------------------------------------------------------------------------------
-
-BITS 64
-
-%define ALIGN_TOP_TO_4K_FOR_PAGING
-
-;
-; Page table big leaf entry attribute:
-; PDPTE 1GB entry or PDE 2MB entry
-;
-%define PAGE_BLE_ATTR (PAGE_SIZE + \
- PAGE_ACCESSED + \
- PAGE_DIRTY + \
- PAGE_READ_WRITE + \
- PAGE_PRESENT)
-
-;
-; Page table non-leaf entry attribute
-;
-%define PAGE_NLE_ATTR (PAGE_ACCESSED + \
- PAGE_READ_WRITE + \
- PAGE_PRESENT)
-
-%define PAGE_NLE(address) (ADDR_OF(address) + \
- PAGE_NLE_ATTR)
-%define PAGE_PDE_2MB(x) ((x << 21) + PAGE_BLE_ATTR)
-
-Pml4:
- ;
- ; PML4 (1 * 512GB entry)
- ;
- DQ PAGE_NLE(Pdp)
- TIMES 0x1000 - ($ - Pml4) DB 0
-
-Pdp:
- ;
- ; Page-directory pointer table (4 * 1GB entries => 4GB)
- ;
- DQ PAGE_NLE(Pd)
- DQ PAGE_NLE(Pd + 0x1000)
- DQ PAGE_NLE(Pd + 0x2000)
- DQ PAGE_NLE(Pd + 0x3000)
- TIMES 0x1000 - ($ - Pdp) DB 0
-
-Pd:
- ;
- ; Page-Directory (2048 * 2MB entries => 4GB)
- ; Four pages below, each is pointed by one entry in Pdp.
- ;
-%assign i 0
-%rep 0x800
- DQ PAGE_PDE_2MB(i)
- %assign i i+1
-%endrep
-
-EndOfPageTables:
--
2.31.1.windows.1
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH v6 4/5] UefiCpuPkg/ResetVector: Modify Page Table in ResetVector
2023-05-15 1:41 [PATCH v6 0/5] UefiCpuPkg/ResetVector: Refine page table creation, and support 5 Level paging Zhiguang Liu
` (2 preceding siblings ...)
2023-05-15 1:41 ` [PATCH v6 3/5] UefiCpuPkg/ResetVector: Combine PageTables1G.asm and PageTables2M.asm Zhiguang Liu
@ 2023-05-15 1:41 ` Zhiguang Liu
2023-05-15 1:41 ` [PATCH v6 5/5] UefiCpuPkg/ResetVector: Support 5 level page table " Zhiguang Liu
2023-05-16 8:06 ` [edk2-devel] [PATCH v6 0/5] UefiCpuPkg/ResetVector: Refine page table creation, and support 5 Level paging Ni, Ray
5 siblings, 0 replies; 7+ messages in thread
From: Zhiguang Liu @ 2023-05-15 1:41 UTC (permalink / raw)
To: devel
Cc: Liu, Zhiguang, Eric Dong, Ray Ni, Rahul Kumar, Gerd Hoffmann,
Debkumar De, Catharine West, Zhiguang Liu
From: "Liu, Zhiguang" <Zhiguang.Liu@intel.com>
In ResetVector, if create page table, its highest address is fixed
because after page table, code layout is fixed(4K for normal code,
and another 4K only contains reset vector code).
Today's implementation organizes the page table as following if 1G
page table is used:
4G-16K: PML4 page (PML4[0] points to 4G-12K)
4G-12K: PDP page
CR3 is set to 4G-16K
When 2M page table is used, the layout is as following:
4G-32K: PML4 page (PML4[0] points to 4G-28K)
4G-28K: PDP page (PDP entries point to PD pages)
4G-24K: PD page mapping 0-1G
4G-20K: PD page mapping 1-2G
4G-16K: PD page mapping 2-3G
4G-12K: PD page mapping 3-4G
CR3 is set to 4G-32K
CR3 doesn't point to a fixed location which is a bit hard to debug at
runtime.
The new page table layout will always put PML4 in highest address
When 1G page table is used, the layout is as following:
4G-16K: PDP page
4G-12K: PML4 page (PML4[0] points to 4G-16K)
When 2M page table is used, the layout is as following:
4G-32K: PD page mapping 0-1G
4G-28K: PD page mapping 1-2G
4G-24K: PD page mapping 2-3G
4G-20K: PD page mapping 3-4G
4G-16K: PDP page (PDP entries point to PD pages)
4G-12K: PML4 page (PML4[0] points to 4G-16K)
CR3 is always set to 4G-12K
So, this patch can improve debuggability by make sure the init
CR3 pointing to a fixed address(4G-12K).
Cc: Eric Dong <eric.dong@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Tested-by: Gerd Hoffmann <kraxel@redhat.com>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Cc: Debkumar De <debkumar.de@intel.com>
Cc: Catharine West <catharine.west@intel.com>
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
---
.../ResetVector/Vtf0/X64/PageTables.asm | 33 ++++++++++---------
1 file changed, 17 insertions(+), 16 deletions(-)
diff --git a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm
index 9b492b063f..d66fb62c34 100644
--- a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm
+++ b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm
@@ -41,13 +41,6 @@ BITS 64
ALIGN 16
-Pml4:
- ;
- ; PML4 (1 * 512GB entry)
- ;
- DQ PAGE_NLE(Pdp)
- TIMES 0x1000 - ($ - Pml4) DB 0
-
%ifdef PAGE_TABLE_1G
Pdp:
;
@@ -59,15 +52,6 @@ Pdp:
%assign i i+1
%endrep
%else
-Pdp:
- ;
- ; Page-directory pointer table (4 * 1GB entries => 4GB)
- ;
- DQ PAGE_NLE(Pd)
- DQ PAGE_NLE(Pd + 0x1000)
- DQ PAGE_NLE(Pd + 0x2000)
- DQ PAGE_NLE(Pd + 0x3000)
- TIMES 0x1000 - ($ - Pdp) DB 0
Pd:
;
@@ -79,5 +63,22 @@ Pd:
DQ PAGE_PDE_2MB(i)
%assign i i+1
%endrep
+Pdp:
+ ;
+ ; Page-directory pointer table (4 * 1GB entries => 4GB)
+ ;
+ DQ PAGE_NLE(Pd)
+ DQ PAGE_NLE(Pd + 0x1000)
+ DQ PAGE_NLE(Pd + 0x2000)
+ DQ PAGE_NLE(Pd + 0x3000)
+ TIMES 0x1000 - ($ - Pdp) DB 0
+
%endif
+
+Pml4:
+ ;
+ ; PML4 (1 * 512GB entry)
+ ;
+ DQ PAGE_NLE(Pdp)
+ TIMES 0x1000 - ($ - Pml4) DB 0
EndOfPageTables:
--
2.31.1.windows.1
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH v6 5/5] UefiCpuPkg/ResetVector: Support 5 level page table in ResetVector
2023-05-15 1:41 [PATCH v6 0/5] UefiCpuPkg/ResetVector: Refine page table creation, and support 5 Level paging Zhiguang Liu
` (3 preceding siblings ...)
2023-05-15 1:41 ` [PATCH v6 4/5] UefiCpuPkg/ResetVector: Modify Page Table in ResetVector Zhiguang Liu
@ 2023-05-15 1:41 ` Zhiguang Liu
2023-05-16 8:06 ` [edk2-devel] [PATCH v6 0/5] UefiCpuPkg/ResetVector: Refine page table creation, and support 5 Level paging Ni, Ray
5 siblings, 0 replies; 7+ messages in thread
From: Zhiguang Liu @ 2023-05-15 1:41 UTC (permalink / raw)
To: devel
Cc: Zhiguang Liu, Eric Dong, Ray Ni, Rahul Kumar, Gerd Hoffmann,
Debkumar De, Catharine West
Add a macro USE_5_LEVEL_PAGE_TABLE to determine whether to create
5 level page table.
If macro USE_5_LEVEL_PAGE_TABLE is defined, PML5Table is created
at (4G-12K), while PML4Table is at (4G-16K). In runtime check, if
5level paging is supported, use PML5Table, otherwise, use PML4Table.
If macro USE_5_LEVEL_PAGE_TABLE is not defined, to save space, 5level
paging is not created, and 4level paging is at (4G-12K) and be used.
V6:
In previous version, I merge code from Ia32\PageTables64.asm into
Ia32\Flat32ToFlat64.asm to reduce files. However, reset vector from
OvmfPkg\Bhyve\ResetVector needs the code from Flat32ToFlat64.asm, and
needs its OneTimeCall SetCr3ForPageTables64. To be compatible,
in this version, I keep the file PageTables64.asm, and implement
5level paging logic there.
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Debkumar De <debkumar.de@intel.com>
Cc: Catharine West <catharine.west@intel.com>
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
---
.../ResetVector/Vtf0/Ia32/PageTables64.asm | 20 +++++++++++++++++++
.../ResetVector/Vtf0/X64/PageTables.asm | 9 +++++++++
2 files changed, 29 insertions(+)
diff --git a/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm b/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm
index f188da20ba..165cebcfaa 100644
--- a/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm
+++ b/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm
@@ -17,8 +17,28 @@ SetCr3ForPageTables64:
;
; These pages are built into the ROM image in X64/PageTables.asm
;
+%ifdef USE_5_LEVEL_PAGE_TABLE
+ mov eax, 0
+ cpuid
+ cmp eax, 07h ; check if basic CPUID leaf contains leaf 07
+ jb NotSupport5LevelPaging ; 5level paging not support, downgrade to 4level paging
+ mov eax, 07h ; check cpuid leaf 7, subleaf 0
+ mov ecx, 0
+ cpuid
+ bt ecx, 16 ; [Bits 16] Supports 5-level paging if 1.
+ jnc NotSupport5LevelPaging ; 5level paging not support, downgrade to 4level paging
+ mov eax, ADDR_OF(Pml5)
+ mov cr3, eax
+ mov eax, cr4
+ bts eax, 12 ; Set LA57=1.
+ mov cr4, eax
+ jmp SetCr3Done
+NotSupport5LevelPaging:
+%endif
+
mov eax, ADDR_OF(Pml4)
mov cr3, eax
+SetCr3Done:
OneTimeCallRet SetCr3ForPageTables64
diff --git a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm
index d66fb62c34..7960b141be 100644
--- a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm
+++ b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm
@@ -81,4 +81,13 @@ Pml4:
;
DQ PAGE_NLE(Pdp)
TIMES 0x1000 - ($ - Pml4) DB 0
+
+%ifdef USE_5_LEVEL_PAGE_TABLE
+Pml5:
+ ;
+ ; Pml5 table (only first entry is present, pointing to Pml4)
+ ;
+ DQ PAGE_NLE(Pml4)
+ TIMES 0x1000 - ($ - Pml5) DB 0
+%endif
EndOfPageTables:
--
2.31.1.windows.1
^ permalink raw reply related [flat|nested] 7+ messages in thread* Re: [edk2-devel] [PATCH v6 0/5] UefiCpuPkg/ResetVector: Refine page table creation, and support 5 Level paging
2023-05-15 1:41 [PATCH v6 0/5] UefiCpuPkg/ResetVector: Refine page table creation, and support 5 Level paging Zhiguang Liu
` (4 preceding siblings ...)
2023-05-15 1:41 ` [PATCH v6 5/5] UefiCpuPkg/ResetVector: Support 5 level page table " Zhiguang Liu
@ 2023-05-16 8:06 ` Ni, Ray
5 siblings, 0 replies; 7+ messages in thread
From: Ni, Ray @ 2023-05-16 8:06 UTC (permalink / raw)
To: devel@edk2.groups.io, Liu, Zhiguang
Reviewed-by: Ray Ni <ray.ni@intel.com>
________________________________________
From: devel@edk2.groups.io <devel@edk2.groups.io> on behalf of Zhiguang Liu <zhiguang.liu@intel.com>
Sent: Monday, May 15, 2023 9:41
To: devel@edk2.groups.io
Cc: Liu, Zhiguang
Subject: [edk2-devel] [PATCH v6 0/5] UefiCpuPkg/ResetVector: Refine page table creation, and support 5 Level paging
This patch set simplify the page table creation code, remove some
hard-code, combine files and support 5 Level paging.
V4:
Refine comments and update below macro names:
PG_NLE -> PAGE_NLE
PTE_2MB -> PDE_2MB
PDP_1G -> PDPTE_1GB
PAGE_BLP_ATTR -> PAGE_BLE_ATTR
No code logic impact
V5:
Update below macro names:
PDE_2MB -> PAGE_PDE_2MB
PDPTE_1GB -> PAGE_PDPTE_1GB
No code logic impact
V6:
Only change the 5th patch to be compatible with reset vector code from
OvmfPkg.
Other patches keep unchagned.
Zhiguang Liu (5):
UefiCpuPkg/ResetVector: Rename macros about page table.
UefiCpuPkg/ResetVector: Simplify page table creation in ResetVector
UefiCpuPkg/ResetVector: Combine PageTables1G.asm and PageTables2M.asm
UefiCpuPkg/ResetVector: Modify Page Table in ResetVector
UefiCpuPkg/ResetVector: Support 5 level page table in ResetVector
.../ResetVector/Vtf0/Ia32/PageTables64.asm | 24 ++++-
UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb | 8 +-
.../ResetVector/Vtf0/X64/PageTables.asm | 93 +++++++++++++++++++
.../ResetVector/Vtf0/X64/PageTables1G.asm | 53 -----------
.../ResetVector/Vtf0/X64/PageTables2M.asm | 60 ------------
5 files changed, 117 insertions(+), 121 deletions(-)
create mode 100644 UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm
delete mode 100644 UefiCpuPkg/ResetVector/Vtf0/X64/PageTables1G.asm
delete mode 100644 UefiCpuPkg/ResetVector/Vtf0/X64/PageTables2M.asm
--
2.31.1.windows.1
^ permalink raw reply [flat|nested] 7+ messages in thread