From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mx.groups.io with SMTP id smtpd.web11.79068.1684114925302985385 for ; Sun, 14 May 2023 18:42:12 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=PgWYxMKd; spf=pass (domain: intel.com, ip: 192.55.52.151, mailfrom: zhiguang.liu@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1684114932; x=1715650932; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=EzxftH4GqRSn6ufWPEPK3/HHW4LwBNRsvmLdInasF2k=; b=PgWYxMKdaeeVF/066Of/nyT0ANnxAGqPf/ySfeaegBBphhjSibNJQWPl 8/WJdgtSrECQEY/D3RulsST7jW6Mh9fn0MSkNtgIIkIjMTyc672b6MapM iyzZRsnXZCJ/OpscwtchY6WfZGt8p76LhU8dWkI+UJ3dpKuGzcv7uFfA0 i05a3ySkm+147DhnsgPS0g7Q15kCS9eziuppe0j6AqwduTVkqzEIexeKl J5FCj7omyznKicmgv1xjOB/GguGG2im+MxSuOzHtzFR6p8SJ3FXXJ1n6t mO4qIrk1qxxnhQpY7bsdU5MrR2Sp8s2L4BbgKCfBf4Hy2b+hrF4z/VCAo Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10710"; a="331457247" X-IronPort-AV: E=Sophos;i="5.99,275,1677571200"; d="scan'208";a="331457247" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 May 2023 18:42:11 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10710"; a="824987120" X-IronPort-AV: E=Sophos;i="5.99,275,1677571200"; d="scan'208";a="824987120" Received: from shwdesfp01.ccr.corp.intel.com ([10.239.158.151]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 May 2023 18:42:09 -0700 From: "Zhiguang Liu" To: devel@edk2.groups.io Cc: "Liu, Zhiguang" , Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann , Debkumar De , Catharine West , Zhiguang Liu Subject: [PATCH v6 4/5] UefiCpuPkg/ResetVector: Modify Page Table in ResetVector Date: Mon, 15 May 2023 09:41:37 +0800 Message-Id: <20230515014138.1321-5-zhiguang.liu@intel.com> X-Mailer: git-send-email 2.31.1.windows.1 In-Reply-To: <20230515014138.1321-1-zhiguang.liu@intel.com> References: <20230515014138.1321-1-zhiguang.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: "Liu, Zhiguang" In ResetVector, if create page table, its highest address is fixed because after page table, code layout is fixed(4K for normal code, and another 4K only contains reset vector code). Today's implementation organizes the page table as following if 1G page table is used: 4G-16K: PML4 page (PML4[0] points to 4G-12K) 4G-12K: PDP page CR3 is set to 4G-16K When 2M page table is used, the layout is as following: 4G-32K: PML4 page (PML4[0] points to 4G-28K) 4G-28K: PDP page (PDP entries point to PD pages) 4G-24K: PD page mapping 0-1G 4G-20K: PD page mapping 1-2G 4G-16K: PD page mapping 2-3G 4G-12K: PD page mapping 3-4G CR3 is set to 4G-32K CR3 doesn't point to a fixed location which is a bit hard to debug at runtime. The new page table layout will always put PML4 in highest address When 1G page table is used, the layout is as following: 4G-16K: PDP page 4G-12K: PML4 page (PML4[0] points to 4G-16K) When 2M page table is used, the layout is as following: 4G-32K: PD page mapping 0-1G 4G-28K: PD page mapping 1-2G 4G-24K: PD page mapping 2-3G 4G-20K: PD page mapping 3-4G 4G-16K: PDP page (PDP entries point to PD pages) 4G-12K: PML4 page (PML4[0] points to 4G-16K) CR3 is always set to 4G-12K So, this patch can improve debuggability by make sure the init CR3 pointing to a fixed address(4G-12K). Cc: Eric Dong Reviewed-by: Ray Ni Cc: Rahul Kumar Tested-by: Gerd Hoffmann Acked-by: Gerd Hoffmann Cc: Debkumar De Cc: Catharine West Signed-off-by: Zhiguang Liu --- .../ResetVector/Vtf0/X64/PageTables.asm | 33 ++++++++++--------- 1 file changed, 17 insertions(+), 16 deletions(-) diff --git a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm index 9b492b063f..d66fb62c34 100644 --- a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm +++ b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm @@ -41,13 +41,6 @@ BITS 64 ALIGN 16 -Pml4: - ; - ; PML4 (1 * 512GB entry) - ; - DQ PAGE_NLE(Pdp) - TIMES 0x1000 - ($ - Pml4) DB 0 - %ifdef PAGE_TABLE_1G Pdp: ; @@ -59,15 +52,6 @@ Pdp: %assign i i+1 %endrep %else -Pdp: - ; - ; Page-directory pointer table (4 * 1GB entries => 4GB) - ; - DQ PAGE_NLE(Pd) - DQ PAGE_NLE(Pd + 0x1000) - DQ PAGE_NLE(Pd + 0x2000) - DQ PAGE_NLE(Pd + 0x3000) - TIMES 0x1000 - ($ - Pdp) DB 0 Pd: ; @@ -79,5 +63,22 @@ Pd: DQ PAGE_PDE_2MB(i) %assign i i+1 %endrep +Pdp: + ; + ; Page-directory pointer table (4 * 1GB entries => 4GB) + ; + DQ PAGE_NLE(Pd) + DQ PAGE_NLE(Pd + 0x1000) + DQ PAGE_NLE(Pd + 0x2000) + DQ PAGE_NLE(Pd + 0x3000) + TIMES 0x1000 - ($ - Pdp) DB 0 + %endif + +Pml4: + ; + ; PML4 (1 * 512GB entry) + ; + DQ PAGE_NLE(Pdp) + TIMES 0x1000 - ($ - Pml4) DB 0 EndOfPageTables: -- 2.31.1.windows.1