[PATCH v6 5/5] UefiCpuPkg/ResetVector: Support 5 level page table in ResetVector

["Zhiguang Liu" <zhiguang.liu@intel.com>]

Add a macro USE_5_LEVEL_PAGE_TABLE to determine whether to create
5 level page table.
If macro USE_5_LEVEL_PAGE_TABLE is defined, PML5Table is created
at (4G-12K), while PML4Table is at (4G-16K). In runtime check, if
5level paging is supported, use PML5Table, otherwise, use PML4Table.
If macro USE_5_LEVEL_PAGE_TABLE is not defined, to save space, 5level
paging is not created, and 4level paging is at (4G-12K) and be used.

V6:
In previous version, I merge code from Ia32\PageTables64.asm into
Ia32\Flat32ToFlat64.asm to reduce files. However, reset vector from
OvmfPkg\Bhyve\ResetVector needs the code from Flat32ToFlat64.asm, and
needs its OneTimeCall SetCr3ForPageTables64. To be compatible,
in this version, I keep the file PageTables64.asm, and implement
5level paging logic there.

Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Debkumar De <debkumar.de@intel.com>
Cc: Catharine West <catharine.west@intel.com>
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
---
 .../ResetVector/Vtf0/Ia32/PageTables64.asm    | 20 +++++++++++++++++++
 .../ResetVector/Vtf0/X64/PageTables.asm       |  9 +++++++++
 2 files changed, 29 insertions(+)

diff --git a/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm b/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm
index f188da20ba..165cebcfaa 100644
--- a/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm
+++ b/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm
@@ -17,8 +17,28 @@ SetCr3ForPageTables64:
     ;
     ; These pages are built into the ROM image in X64/PageTables.asm
     ;
+%ifdef USE_5_LEVEL_PAGE_TABLE
+    mov     eax, 0
+    cpuid
+    cmp     eax, 07h                    ; check if basic CPUID leaf contains leaf 07
+    jb      NotSupport5LevelPaging      ; 5level paging not support, downgrade to 4level paging
+    mov     eax, 07h                    ; check cpuid leaf 7, subleaf 0
+    mov     ecx, 0
+    cpuid
+    bt      ecx, 16                     ; [Bits 16] Supports 5-level paging if 1.
+    jnc     NotSupport5LevelPaging      ; 5level paging not support, downgrade to 4level paging
+    mov     eax, ADDR_OF(Pml5)
+    mov     cr3, eax
+    mov     eax, cr4
+    bts     eax, 12                     ; Set LA57=1.
+    mov     cr4, eax
+    jmp     SetCr3Done
+NotSupport5LevelPaging:
+%endif
+
     mov     eax, ADDR_OF(Pml4)
     mov     cr3, eax
+SetCr3Done:
 
     OneTimeCallRet SetCr3ForPageTables64
 
diff --git a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm
index d66fb62c34..7960b141be 100644
--- a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm
+++ b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm
@@ -81,4 +81,13 @@ Pml4:
     ;
     DQ      PAGE_NLE(Pdp)
     TIMES   0x1000 - ($ - Pml4) DB 0
+
+%ifdef USE_5_LEVEL_PAGE_TABLE
+Pml5:
+    ;
+    ; Pml5 table (only first entry is present, pointing to Pml4)
+    ;
+    DQ      PAGE_NLE(Pml4)
+    TIMES   0x1000 - ($ - Pml5) DB 0
+%endif
 EndOfPageTables:
-- 
2.31.1.windows.1