From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mx.groups.io with SMTP id smtpd.web11.79068.1684114925302985385 for ; Sun, 14 May 2023 18:42:15 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=oDVV6A1A; spf=pass (domain: intel.com, ip: 192.55.52.151, mailfrom: zhiguang.liu@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1684114934; x=1715650934; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ftqs7msdC3Rmz866aIyFfIZ2xKJo/AVqdQxRja9xkG0=; b=oDVV6A1A+OJAi7HfwaBgR74q3uAh6GVu4kZvKWRLfsNlTeJ8gXXXmX/L Mu9NndjauaBX7YFi5c4YOWyitKs+Hoo6Si+RwwdeBBwSCSSG38eGpQETA HgzcoYW1STETQ4ZY8oFj+Env/exIhcFFmYo3U6IJiZMXlQNm8gQb9Mq3V 6IMe/4kMn0GgJvs2w2kv8P5UbneR9lG0KSisr0gUxkgfD0SuNH23jQ1wu rAzgk0Qf7c33Yz5+me8+qIS+65AC9tajSSZ4oZesBi5Rkz/VulvF0zz9j XgdxExEdyd9vN8mn6YXKK3C6AvkDwmT+vLcjo9m9BLmMInk/I5OSLa/6V w==; X-IronPort-AV: E=McAfee;i="6600,9927,10710"; a="331457262" X-IronPort-AV: E=Sophos;i="5.99,275,1677571200"; d="scan'208";a="331457262" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 May 2023 18:42:14 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10710"; a="824987154" X-IronPort-AV: E=Sophos;i="5.99,275,1677571200"; d="scan'208";a="824987154" Received: from shwdesfp01.ccr.corp.intel.com ([10.239.158.151]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 May 2023 18:42:12 -0700 From: "Zhiguang Liu" To: devel@edk2.groups.io Cc: Zhiguang Liu , Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann , Debkumar De , Catharine West Subject: [PATCH v6 5/5] UefiCpuPkg/ResetVector: Support 5 level page table in ResetVector Date: Mon, 15 May 2023 09:41:38 +0800 Message-Id: <20230515014138.1321-6-zhiguang.liu@intel.com> X-Mailer: git-send-email 2.31.1.windows.1 In-Reply-To: <20230515014138.1321-1-zhiguang.liu@intel.com> References: <20230515014138.1321-1-zhiguang.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add a macro USE_5_LEVEL_PAGE_TABLE to determine whether to create 5 level page table. If macro USE_5_LEVEL_PAGE_TABLE is defined, PML5Table is created at (4G-12K), while PML4Table is at (4G-16K). In runtime check, if 5level paging is supported, use PML5Table, otherwise, use PML4Table. If macro USE_5_LEVEL_PAGE_TABLE is not defined, to save space, 5level paging is not created, and 4level paging is at (4G-12K) and be used. V6: In previous version, I merge code from Ia32\PageTables64.asm into Ia32\Flat32ToFlat64.asm to reduce files. However, reset vector from OvmfPkg\Bhyve\ResetVector needs the code from Flat32ToFlat64.asm, and needs its OneTimeCall SetCr3ForPageTables64. To be compatible, in this version, I keep the file PageTables64.asm, and implement 5level paging logic there. Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann Cc: Debkumar De Cc: Catharine West Signed-off-by: Zhiguang Liu --- .../ResetVector/Vtf0/Ia32/PageTables64.asm | 20 +++++++++++++++++++ .../ResetVector/Vtf0/X64/PageTables.asm | 9 +++++++++ 2 files changed, 29 insertions(+) diff --git a/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm b/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm index f188da20ba..165cebcfaa 100644 --- a/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm +++ b/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm @@ -17,8 +17,28 @@ SetCr3ForPageTables64: ; ; These pages are built into the ROM image in X64/PageTables.asm ; +%ifdef USE_5_LEVEL_PAGE_TABLE + mov eax, 0 + cpuid + cmp eax, 07h ; check if basic CPUID leaf contains leaf 07 + jb NotSupport5LevelPaging ; 5level paging not support, downgrade to 4level paging + mov eax, 07h ; check cpuid leaf 7, subleaf 0 + mov ecx, 0 + cpuid + bt ecx, 16 ; [Bits 16] Supports 5-level paging if 1. + jnc NotSupport5LevelPaging ; 5level paging not support, downgrade to 4level paging + mov eax, ADDR_OF(Pml5) + mov cr3, eax + mov eax, cr4 + bts eax, 12 ; Set LA57=1. + mov cr4, eax + jmp SetCr3Done +NotSupport5LevelPaging: +%endif + mov eax, ADDR_OF(Pml4) mov cr3, eax +SetCr3Done: OneTimeCallRet SetCr3ForPageTables64 diff --git a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm index d66fb62c34..7960b141be 100644 --- a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm +++ b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm @@ -81,4 +81,13 @@ Pml4: ; DQ PAGE_NLE(Pdp) TIMES 0x1000 - ($ - Pml4) DB 0 + +%ifdef USE_5_LEVEL_PAGE_TABLE +Pml5: + ; + ; Pml5 table (only first entry is present, pointing to Pml4) + ; + DQ PAGE_NLE(Pml4) + TIMES 0x1000 - ($ - Pml5) DB 0 +%endif EndOfPageTables: -- 2.31.1.windows.1