From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mx.groups.io with SMTP id smtpd.web10.79852.1684116965727635794 for ; Sun, 14 May 2023 19:16:06 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=PlMCd3rN; spf=pass (domain: intel.com, ip: 134.134.136.100, mailfrom: jiaxin.wu@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1684116965; x=1715652965; h=from:to:subject:date:message-id; bh=Ze8XIBt0thh/PyqLoKRmaCaRrqJopceyhzGZYUdy1J4=; b=PlMCd3rNDH5O51zdyVu5owdhCE/DeWMqYF9sICY/hJ8Ky3eIEp0Uf8BI OvPcKGfzlGXHFnkK6QwvkTKEEg0Hxmfjkm2rmYAAXOaB6VwRPHrn6tdN7 S3OhXUniyFIsmAbT4yXErxB2iYFuSTAQAEjLSRDvKt54gcXqTSMJ7LpZb OH3tgJcI+MFHhDxnxNDDV95Iv0as8E7M/7ZC5TUcHS6Uu9zt+B9ye+xIz sDgGVf3M2K4oAmE9MbYNL5rYXZEsWCXOOcG42VKiwVoKDXugk9LdDZAZ/ Ra4oPvptR1GVXp61hEdq8dgQLB+64+uKcLBomFFfncKoptxYYWRXVRZ4z g==; X-IronPort-AV: E=McAfee;i="6600,9927,10710"; a="416739555" X-IronPort-AV: E=Sophos;i="5.99,275,1677571200"; d="scan'208";a="416739555" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 May 2023 19:16:05 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10710"; a="947260449" X-IronPort-AV: E=Sophos;i="5.99,275,1677571200"; d="scan'208";a="947260449" Received: from sh1gapp1009.ccr.corp.intel.com ([10.239.189.219]) by fmsmga006.fm.intel.com with ESMTP; 14 May 2023 19:16:04 -0700 From: "Wu, Jiaxin" To: devel@edk2.groups.io Subject: [PATCH v3 0/5] Target to enable paging from temporary RAM Done Date: Mon, 15 May 2023 10:15:56 +0800 Message-Id: <20230515021601.6244-1-jiaxin.wu@intel.com> X-Mailer: git-send-email 2.16.2.windows.1 For arch X64, system will enable the page table in SPI to cover 0-512G range via CR4.PAE & MSR.LME & CR0.PG & CR3 setting. Existing code doesn't cover the higher address access above 512G before memory-discovered callback. This series patches provide the solution to enable paging from temporary RAM Done. Jiaxin Wu (5): UefiCpuPkg/SecCore: Migrate page table to permanent memory UefiCpuPkg/CpuMpPei: Conditionally enable PAE paging in 32bit mode MdeModulePkg/DxeIpl: Align Page table Level setting with previous level. OvmfPkg: Add CpuPageTableLib required by SecCore & CpuMpPei UefiPayloadPkg: Add CpuPageTableLib required by SecCore & CpuMpPei MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c | 36 ++-- OvmfPkg/AmdSev/AmdSevX64.dsc | 2 +- OvmfPkg/CloudHv/CloudHvX64.dsc | 2 +- OvmfPkg/IntelTdx/IntelTdxX64.dsc | 3 +- OvmfPkg/Microvm/MicrovmX64.dsc | 2 +- OvmfPkg/OvmfPkgIa32.dsc | 1 + OvmfPkg/OvmfPkgIa32X64.dsc | 2 +- OvmfPkg/OvmfPkgX64.dsc | 3 +- OvmfPkg/OvmfXen.dsc | 2 +- UefiCpuPkg/CpuMpPei/CpuMpPei.h | 1 + UefiCpuPkg/CpuMpPei/CpuMpPei.inf | 1 + UefiCpuPkg/CpuMpPei/CpuPaging.c | 202 ++++++++--------------- UefiCpuPkg/SecCore/SecCore.inf | 1 + UefiCpuPkg/SecCore/SecCoreNative.inf | 1 + UefiCpuPkg/SecCore/SecMain.c | 147 +++++++++++++++++ UefiCpuPkg/SecCore/SecMain.h | 4 + UefiPayloadPkg/UefiPayloadPkg.dsc | 2 +- 17 files changed, 261 insertions(+), 151 deletions(-) -- 2.16.2.windows.1