From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mx.groups.io with SMTP id smtpd.web10.79852.1684116965727635794 for ; Sun, 14 May 2023 19:16:11 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=cj7HtEm3; spf=pass (domain: intel.com, ip: 134.134.136.100, mailfrom: jiaxin.wu@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1684116971; x=1715652971; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=G+1b2i9Vh7BQM4h292qGw5rodzdJ301758LwaO9JmHs=; b=cj7HtEm3S5S/sSTCVGzHaFxeH3MCxiy/xrPwTsu9Yd80YPK+jfKT7ZdX ebl5YNwv0kWBKRaFSDFMQvmPjFLD2CbaZdN4k6Ww/z0fV+PmB7xqYaxdh g/58c+U/FIcfT0BlSMdJhrpqjw9JMdZyYP3oILLoxIjZ4mLqhgZ4MKiGN 5NqP4O/iGS5MMuDihTjfs6d8M7Y8p92MkJceNZu6oo/WRxctpBZae0g0S YMsfk9VOnceQZRSr+2yXo6wYW2qVsaNnvIRLPmRQDSFkUNehrLUqzy2JB 0GoEElWCxFHcRDbXlxOpRvzqcJ6sRwP8ynlh6IrtoGfbUs/jLNRy+1uQh Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10710"; a="416739593" X-IronPort-AV: E=Sophos;i="5.99,275,1677571200"; d="scan'208";a="416739593" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 May 2023 19:16:11 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10710"; a="947260467" X-IronPort-AV: E=Sophos;i="5.99,275,1677571200"; d="scan'208";a="947260467" Received: from sh1gapp1009.ccr.corp.intel.com ([10.239.189.219]) by fmsmga006.fm.intel.com with ESMTP; 14 May 2023 19:16:09 -0700 From: "Wu, Jiaxin" To: devel@edk2.groups.io Cc: Dandan Bi , Liming Gao , Eric Dong , Ray Ni , Zeng Star , Gerd Hoffmann , Rahul Kumar Subject: [PATCH v3 3/5] MdeModulePkg/DxeIpl: Align Page table Level setting with previous level. Date: Mon, 15 May 2023 10:15:59 +0800 Message-Id: <20230515021601.6244-4-jiaxin.wu@intel.com> X-Mailer: git-send-email 2.16.2.windows.1 In-Reply-To: <20230515021601.6244-1-jiaxin.wu@intel.com> References: <20230515021601.6244-1-jiaxin.wu@intel.com> System paging 5 level enabled or not can be checked via CR4.LA57, system preferred Page table Level (PcdUse5LevelPageTable) must align with previous level for 64bit long mode. This patch is to do the wise check: If cpu has already run in 64bit long mode PEI, Page table Level in DXE must align with previous level. If cpu runs in 32bit protected mode PEI, Page table Level in DXE is decided by PCD and feature capability. Cc: Dandan Bi Cc: Liming Gao Cc: Eric Dong Cc: Ray Ni Cc: Zeng Star Cc: Gerd Hoffmann Cc: Rahul Kumar Signed-off-by: Jiaxin Wu --- MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c | 36 ++++++++++++++++-------- 1 file changed, 24 insertions(+), 12 deletions(-) diff --git a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c index 18b121d768..980c2002d4 100644 --- a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c +++ b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c @@ -737,22 +737,34 @@ CreateIdentityMappingPageTables ( } else { PhysicalAddressBits = 36; } } - Page5LevelSupport = FALSE; - if (PcdGetBool (PcdUse5LevelPageTable)) { - AsmCpuidEx ( - CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, - CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO, - NULL, - NULL, - &EcxFlags.Uint32, - NULL - ); - if (EcxFlags.Bits.FiveLevelPage != 0) { - Page5LevelSupport = TRUE; + if (sizeof (UINTN) == sizeof (UINT64)) { + // + // If cpu has already run in 64bit long mode PEI, Page table Level in DXE must align with previous level. + // + Cr4.UintN = AsmReadCr4 (); + Page5LevelSupport = (Cr4.Bits.LA57 != 0); + ASSERT (PcdGetBool (PcdUse5LevelPageTable) == Page5LevelSupport); + } else { + // + // If cpu runs in 32bit protected mode PEI, Page table Level in DXE is decided by PCD and feature capability. + // + Page5LevelSupport = FALSE; + if (PcdGetBool (PcdUse5LevelPageTable)) { + AsmCpuidEx ( + CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, + CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO, + NULL, + NULL, + &EcxFlags.Uint32, + NULL + ); + if (EcxFlags.Bits.FiveLevelPage != 0) { + Page5LevelSupport = TRUE; + } } } DEBUG ((DEBUG_INFO, "AddressBits=%u 5LevelPaging=%u 1GPage=%u\n", PhysicalAddressBits, Page5LevelSupport, Page1GSupport)); -- 2.16.2.windows.1