From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by mx.groups.io with SMTP id smtpd.web11.16322.1684829472701219872 for ; Tue, 23 May 2023 01:11:12 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=FA53YxbY; spf=pass (domain: intel.com, ip: 192.55.52.120, mailfrom: w.sheng@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1684829472; x=1716365472; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=EdmECrBjErg8BqiZWDp0P1iN9ehWq/xIzrw4exIfQJ0=; b=FA53YxbYn4TNB7cCK62M6iXsAtVJcUAa+8eqUBpvl2n7pgTeO+SEGCrz XSHBtLms1+HeVUeAPlNDOnWoHGXZrtmvJoOzNnNajMxQYtZBpuNU6pZEG ynYqp6HZrVqESPOLvh+omKSo+3xS0ZRIeoiYv69uj+BGvuB24Jz5KMoH0 zqjq5FniOzbpiAY7tm4MUupMEzs0PywiwJDgCf4nIORB1hMKk65hWKkdG kfJVJVz4GZfOGn8YlSsoqTf6iXQck3GK9Wvj5lKepQqJFbttLZRLw8itC jQUCxZ798Aioov+ETnxjDvYNyGjkgiTuUZtBpwp8pK1BfdxZDGjz/kGex g==; X-IronPort-AV: E=McAfee;i="6600,9927,10718"; a="352020358" X-IronPort-AV: E=Sophos;i="6.00,185,1681196400"; d="scan'208";a="352020358" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 May 2023 01:11:12 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10718"; a="654276288" X-IronPort-AV: E=Sophos;i="6.00,185,1681196400"; d="scan'208";a="654276288" Received: from shwdesssddpdwei.ccr.corp.intel.com ([10.239.157.28]) by orsmga003.jf.intel.com with ESMTP; 23 May 2023 01:11:10 -0700 From: "Sheng Wei" To: devel@edk2.groups.io Cc: Ray Ni , Rangasai V Chaganty , Jenny Huang , Robert Kowalewski Subject: [PATCH] IntelSiliconPkg/IntelVTdDmarPei: Fix build error when disable optimization Date: Tue, 23 May 2023 16:11:07 +0800 Message-Id: <20230523081107.376-1-w.sheng@intel.com> X-Mailer: git-send-email 2.26.2.windows.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable MSFT:*_*_*_CC_FLAGS =3D /Od will disable build optimization. Signed-off-by: Sheng Wei Cc: Ray Ni Cc: Rangasai V Chaganty Cc: Jenny Huang Cc: Robert Kowalewski --- .../VTd/IntelVTdDmarPei/IntelVTdDmar.c | 43 +++++++++++++------ 1 file changed, 31 insertions(+), 12 deletions(-) diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/Inte= lVTdDmar.c b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/Inte= lVTdDmar.c index ae9135010..e1b867973 100644 --- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/IntelVTdDma= r.c +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/IntelVTdDma= r.c @@ -242,6 +242,7 @@ SubmitQueuedInvalidationDescriptor ( VTD_IQA_REG IqaReg;=0D VTD_IQT_REG IqtReg;=0D VTD_IQH_REG IqhReg;=0D + UINT64 IQBassAddress;=0D =0D if (Desc =3D=3D NULL) {=0D return EFI_INVALID_PARAMETER;=0D @@ -249,19 +250,29 @@ SubmitQueuedInvalidationDescriptor ( =0D VtdUnitBaseAddress =3D VTdUnitInfo->VtdUnitBaseAddress;=0D IqaReg.Uint64 =3D MmioRead64 (VtdUnitBaseAddress + R_IQA_REG);=0D - if (IqaReg.Bits.IQA =3D=3D 0) {=0D + //=0D + // Get IQA_REG.IQA (Invalidation Queue Base Address)=0D + //=0D + IQBassAddress =3D RShiftU64 (IqaReg.Uint64, 12);=0D + if (IQBassAddress =3D=3D 0) {=0D DEBUG ((DEBUG_ERROR,"Invalidation Queue Buffer not ready [0x%lx]\n", I= qaReg.Uint64));=0D return EFI_NOT_READY;=0D }=0D IqtReg.Uint64 =3D MmioRead64 (VtdUnitBaseAddress + R_IQT_REG);=0D =0D - if (IqaReg.Bits.DW =3D=3D 0) {=0D + //=0D + // Check IQA_REG.DW (Descriptor Width)=0D + //=0D + if ((IqaReg.Uint64 & BIT11) =3D=3D 0) {=0D //=0D // 128-bit descriptor=0D //=0D QueueSize =3D (UINTN) (1 << (IqaReg.Bits.QS + 8));=0D - Qi128Desc =3D (QI_DESC *) (UINTN) (IqaReg.Bits.IQA << VTD_PAGE_SHIFT);= =0D - QueueTail =3D (UINTN) IqtReg.Bits128Desc.QT;=0D + Qi128Desc =3D (QI_DESC *) (UINTN) LShiftU64 (IQBassAddress, VTD_PAGE_S= HIFT);=0D + //=0D + // Get IQT_REG.QT for 128-bit descriptors=0D + //=0D + QueueTail =3D (UINTN) (RShiftU64 (IqtReg.Uint64, 4) & 0x7FFF);=0D Qi128Desc +=3D QueueTail;=0D Qi128Desc->Low =3D Desc->Uint64[0];=0D Qi128Desc->High =3D Desc->Uint64[1];=0D @@ -274,14 +285,18 @@ SubmitQueuedInvalidationDescriptor ( Desc->Uint64[0],=0D Desc->Uint64[1]));=0D =0D - IqtReg.Bits128Desc.QT =3D QueueTail;=0D + IqtReg.Uint64 &=3D ~(0x7FFF << 4);=0D + IqtReg.Uint64 |=3D LShiftU64 (QueueTail, 4);=0D } else {=0D //=0D // 256-bit descriptor=0D //=0D QueueSize =3D (UINTN) (1 << (IqaReg.Bits.QS + 7));=0D - Qi256Desc =3D (QI_256_DESC *) (UINTN) (IqaReg.Bits.IQA << VTD_PAGE_SHI= FT);=0D - QueueTail =3D (UINTN) IqtReg.Bits256Desc.QT;=0D + Qi256Desc =3D (QI_256_DESC *) (UINTN) LShiftU64 (IQBassAddress, VTD_PA= GE_SHIFT);=0D + //=0D + // Get IQT_REG.QT for 256-bit descriptors=0D + //=0D + QueueTail =3D (UINTN) (RShiftU64 (IqtReg.Uint64, 5) & 0x3FFF);=0D Qi256Desc +=3D QueueTail;=0D Qi256Desc->Uint64[0] =3D Desc->Uint64[0];=0D Qi256Desc->Uint64[1] =3D Desc->Uint64[1];=0D @@ -298,7 +313,8 @@ SubmitQueuedInvalidationDescriptor ( Desc->Uint64[2],=0D Desc->Uint64[3]));=0D =0D - IqtReg.Bits256Desc.QT =3D QueueTail;=0D + IqtReg.Uint64 &=3D ~(0x3FFF << 5);=0D + IqtReg.Uint64 |=3D LShiftU64 (QueueTail, 5);=0D }=0D =0D //=0D @@ -315,10 +331,13 @@ SubmitQueuedInvalidationDescriptor ( }=0D =0D IqhReg.Uint64 =3D MmioRead64 (VtdUnitBaseAddress + R_IQH_REG);=0D - if (IqaReg.Bits.DW =3D=3D 0) {=0D - QueueHead =3D (UINTN) IqhReg.Bits128Desc.QH;=0D + //=0D + // Check IQA_REG.DW (Descriptor Width) and get IQH_REG.QH=0D + //=0D + if ((IqaReg.Uint64 & BIT11) =3D=3D 0) {=0D + QueueHead =3D (UINTN) (RShiftU64 (IqhReg.Uint64, 4) & 0x7FFF);=0D } else {=0D - QueueHead =3D (UINTN) IqhReg.Bits256Desc.QH;=0D + QueueHead =3D (UINTN) (RShiftU64 (IqhReg.Uint64, 5) & 0x3FFF);=0D }=0D } while (QueueTail !=3D QueueHead);=0D =0D @@ -410,7 +429,7 @@ InvalidateIOTLB ( // Queued Invalidation=0D //=0D CapReg.Uint64 =3D MmioRead64 (VTdUnitInfo->VtdUnitBaseAddress + R_CAP_= REG);=0D - QiDesc.Uint64[0] =3D QI_IOTLB_DID(0) | QI_IOTLB_DR(CAP_READ_DRAIN(CapR= eg.Uint64)) | QI_IOTLB_DW(CAP_WRITE_DRAIN(CapReg.Uint64)) | QI_IOTLB_GRAN(1= ) | QI_IOTLB_TYPE;=0D + QiDesc.Uint64[0] =3D QI_IOTLB_DID(0) | (CapReg.Bits.DRD ? QI_IOTLB_DR(= 1) : QI_IOTLB_DR(0)) | (CapReg.Bits.DWD ? QI_IOTLB_DW(1) : QI_IOTLB_DW(0)) = | QI_IOTLB_GRAN(1) | QI_IOTLB_TYPE;=0D QiDesc.Uint64[1] =3D QI_IOTLB_ADDR(0) | QI_IOTLB_IH(0) | QI_IOTLB_AM(0= );=0D QiDesc.Uint64[2] =3D 0;=0D QiDesc.Uint64[3] =3D 0;=0D --=20 2.26.2.windows.1