From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pf1-f171.google.com (mail-pf1-f171.google.com [209.85.210.171]) by mx.groups.io with SMTP id smtpd.web10.1083.1685143062920599913 for ; Fri, 26 May 2023 16:17:42 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@ventanamicro.com header.s=google header.b=I0cQs7fx; spf=pass (domain: ventanamicro.com, ip: 209.85.210.171, mailfrom: tphan@ventanamicro.com) Received: by mail-pf1-f171.google.com with SMTP id d2e1a72fcca58-64d577071a6so1791016b3a.1 for ; Fri, 26 May 2023 16:17:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1685143062; x=1687735062; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=JzkeFROntcK9yi4m5QRewONx80t20dQk/DnJ/bOeGk8=; b=I0cQs7fxVkxMejgOinO8MVD4xlqyC6iLIYjhJ8bnrsvzoH5UNz4F94x95qDuljU2ss nwV6k0ZcWQNjD1saie521QfQXW0+Xp4nk9ks3+KVIY7dRcoJr+rVyVkHY1e6DKRrpuSF ERKAuAUN1dBElv7lLZnYTYX5a/NM93ntmhCTW3P+BnzQrKATiRaFoum+Lo04CHitL9Ov HSMvtP/AXwo8XR2157MdfRM1j6cQHo9XVAn72ig4dMA/jrBbZqQj5jUxCeQnNaFEleC/ Ocd1XpN/uUa1ZWEmXcCZH9cxNwhz0UPpMNvU/xjRuo0BbXXMrXWDOOKbq+bsStomNPPq vuIg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685143062; x=1687735062; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JzkeFROntcK9yi4m5QRewONx80t20dQk/DnJ/bOeGk8=; b=DBYfWyPO3mtT+SwP6wizfv2QQHePIl1agoabFyaOlt5FW6d6WT4a7AhFQezFQhLKxl fMN7XK3zm/X0UbM/jfOqkmOhQr3pFMXd5+BrsbdGo9M73iwDLJDUMXsmFmxfGykg2DbK h5fY1i4RMjZQDofwY3RlHv/h6FQqaMHR05AZXJQBsbLcuFRSeyFtHNRTC8fhaxdAWXlH 49VWrXuP6giT6Ru4dnk7yoFa/oOu3Tv+AxJj8o9kRaAll13tnGdOYkRkonUks6yIvdqT oupbw2e+QWyLMMtspvKPngcH/pVTP6QOZCdVYmezbd+F/a/+rKwUdAM6Y9HBc+htAiGP 3jFA== X-Gm-Message-State: AC+VfDzYkXG/2iyL8Js5IpkPtDhNUvVJapIqzOInHNMco2+TzcyVgUyn wzx1+0WaU+9aXomCZcf2y0XMUUKqrr36DYaIptw= X-Google-Smtp-Source: ACHHUZ7hz4B5XvWh99Ubq478w6Ytqw3okncJYjFVGH75mr79yV/n0SItKbshQtRRI/lc1E1W+kCmbQ== X-Received: by 2002:a05:6a20:7d88:b0:10c:29e5:941e with SMTP id v8-20020a056a207d8800b0010c29e5941emr1096765pzj.59.1685143062108; Fri, 26 May 2023 16:17:42 -0700 (PDT) Return-Path: Received: from localhost.localdomain (c-174-50-177-95.hsd1.ca.comcast.net. [174.50.177.95]) by smtp.gmail.com with ESMTPSA id k3-20020aa792c3000000b005d22639b577sm3106308pfa.165.2023.05.26.16.17.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 May 2023 16:17:41 -0700 (PDT) From: "Tuan Phan" To: devel@edk2.groups.io Cc: michael.d.kinney@intel.com, gaoliming@byosoft.com.cn, zhiguang.liu@intel.com, sunilvl@ventanamicro.com, git@danielschaefer.me, andrei.warkentin@intel.com, Tuan Phan Subject: [PATCH v3 2/7] MdePkg/Register: RISC-V: Add satp mode bits shift definition Date: Fri, 26 May 2023 16:17:28 -0700 Message-Id: <20230526231733.6755-3-tphan@ventanamicro.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230526231733.6755-1-tphan@ventanamicro.com> References: <20230526231733.6755-1-tphan@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable The satp mode bits shift is used cross modules. It should be defined in one place. Signed-off-by: Tuan Phan Reviewed-by: Andrei Warkentin --- MdePkg/Include/Register/RiscV64/RiscVEncoding.h | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/MdePkg/Include/Register/RiscV64/RiscVEncoding.h b/MdePkg/Inclu= de/Register/RiscV64/RiscVEncoding.h index 5c2989b797bf..2bde8db478ff 100644 --- a/MdePkg/Include/Register/RiscV64/RiscVEncoding.h +++ b/MdePkg/Include/Register/RiscV64/RiscVEncoding.h @@ -58,9 +58,10 @@ #define PRV_S 1UL=0D #define PRV_M 3UL=0D =0D -#define SATP64_MODE 0xF000000000000000ULL=0D -#define SATP64_ASID 0x0FFFF00000000000ULL=0D -#define SATP64_PPN 0x00000FFFFFFFFFFFULL=0D +#define SATP64_MODE 0xF000000000000000ULL=0D +#define SATP64_MODE_SHIFT 60=0D +#define SATP64_ASID 0x0FFFF00000000000ULL=0D +#define SATP64_PPN 0x00000FFFFFFFFFFFULL=0D =0D #define SATP_MODE_OFF 0UL=0D #define SATP_MODE_SV32 1UL=0D --=20 2.25.1