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From: "Tuan Phan" <tphan@ventanamicro.com>
To: devel@edk2.groups.io
Cc: michael.d.kinney@intel.com, gaoliming@byosoft.com.cn,
	zhiguang.liu@intel.com, sunilvl@ventanamicro.com,
	git@danielschaefer.me, andrei.warkentin@intel.com,
	Tuan Phan <tphan@ventanamicro.com>
Subject: [PATCH v3 4/7] OvmfPkg/RiscVVirt: Remove satp bare mode setting
Date: Fri, 26 May 2023 16:17:30 -0700	[thread overview]
Message-ID: <20230526231733.6755-5-tphan@ventanamicro.com> (raw)
In-Reply-To: <20230526231733.6755-1-tphan@ventanamicro.com>

MMU now is initialized in CpuDxe. There is no point to set satp to bare
mode as that should be the default mode when booting edk2.

Signed-off-by: Tuan Phan <tphan@ventanamicro.com>
Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com>
---
 OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc |  1 +
 OvmfPkg/RiscVVirt/Sec/Memory.c      | 18 ++----------------
 2 files changed, 3 insertions(+), 16 deletions(-)

diff --git a/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc b/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
index 731f54f73f81..bc204ba5fe52 100644
--- a/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
+++ b/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
@@ -83,6 +83,7 @@
   # RISC-V Architectural Libraries
   CpuExceptionHandlerLib|UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/BaseRiscV64CpuExceptionHandlerLib.inf
   RiscVSbiLib|MdePkg/Library/BaseRiscVSbiLib/BaseRiscVSbiLib.inf
+  RiscVMmuLib|UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
   PlatformBootManagerLib|OvmfPkg/RiscVVirt/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
   ResetSystemLib|OvmfPkg/RiscVVirt/Library/ResetSystemLib/BaseResetSystemLib.inf
 
diff --git a/OvmfPkg/RiscVVirt/Sec/Memory.c b/OvmfPkg/RiscVVirt/Sec/Memory.c
index 0e2690c73687..aad71ee5dcbb 100644
--- a/OvmfPkg/RiscVVirt/Sec/Memory.c
+++ b/OvmfPkg/RiscVVirt/Sec/Memory.c
@@ -85,21 +85,6 @@ AddMemoryRangeHob (
   AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
 }
 
-/**
-  Configure MMU
-**/
-STATIC
-VOID
-InitMmu (
-  )
-{
-  //
-  // Set supervisor translation mode to Bare mode
-  //
-  RiscVSetSupervisorAddressTranslationRegister ((UINT64)SATP_MODE_OFF << 60);
-  DEBUG ((DEBUG_INFO, "%a: Set Supervisor address mode to bare-metal mode.\n", __func__));
-}
-
 /**
   Publish system RAM and reserve memory regions.
 
@@ -327,7 +312,8 @@ MemoryPeimInitialization (
 
   AddReservedMemoryMap (FdtPointer);
 
-  InitMmu ();
+  /* Make sure SEC is booting with bare mode */
+  ASSERT ((RiscVGetSupervisorAddressTranslationRegister () & SATP64_MODE) == (SATP_MODE_OFF << SATP64_MODE_SHIFT));
 
   BuildMemoryTypeInformationHob ();
 
-- 
2.25.1


  parent reply	other threads:[~2023-05-26 23:17 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-05-26 23:17 [PATCH v3 0/7] RISC-V: MMU support Tuan Phan
2023-05-26 23:17 ` [PATCH v3 1/7] MdePkg/BaseLib: RISC-V: Support getting satp register value Tuan Phan
2023-06-06 10:29   ` Sunil V L
2023-05-26 23:17 ` [PATCH v3 2/7] MdePkg/Register: RISC-V: Add satp mode bits shift definition Tuan Phan
2023-06-06 10:31   ` Sunil V L
2023-05-26 23:17 ` [PATCH v3 3/7] UefiCpuPkg: RISC-V: Support MMU with SV39/48/57 mode Tuan Phan
2023-05-26 23:17 ` Tuan Phan [this message]
2023-06-06 10:35   ` [PATCH v3 4/7] OvmfPkg/RiscVVirt: Remove satp bare mode setting Sunil V L
2023-05-26 23:17 ` [PATCH v3 5/7] OvmfPkg/RiscVVirt: VirtNorFlashPlatformLib: Fix wrong flash size Tuan Phan
2023-06-06 10:34   ` Sunil V L
2023-05-26 23:17 ` [PATCH v3 6/7] OvmfPkg/VirtNorFlashDxe: Not add memory space if it exists Tuan Phan
2023-05-26 23:17 ` [PATCH v3 7/7] OvmfPkg/RiscVVirt: SEC: Add IO memory resource hob for platform devices Tuan Phan
2023-05-29 14:07   ` [edk2-devel] " Ard Biesheuvel
2023-05-30 17:37     ` Tuan Phan
     [not found]     ` <1763FC7B83488280.11718@groups.io>
2023-06-22 18:41       ` Tuan Phan
2023-06-22 20:27         ` Tuan Phan
2023-12-08  7:36           ` Andrei Warkentin
2023-12-14 18:59             ` Tuan Phan

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