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[174.50.177.95]) by smtp.gmail.com with ESMTPSA id k3-20020aa792c3000000b005d22639b577sm3106308pfa.165.2023.05.26.16.17.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 May 2023 16:17:44 -0700 (PDT) From: "Tuan Phan" To: devel@edk2.groups.io Cc: michael.d.kinney@intel.com, gaoliming@byosoft.com.cn, zhiguang.liu@intel.com, sunilvl@ventanamicro.com, git@danielschaefer.me, andrei.warkentin@intel.com, Tuan Phan Subject: [PATCH v3 4/7] OvmfPkg/RiscVVirt: Remove satp bare mode setting Date: Fri, 26 May 2023 16:17:30 -0700 Message-Id: <20230526231733.6755-5-tphan@ventanamicro.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230526231733.6755-1-tphan@ventanamicro.com> References: <20230526231733.6755-1-tphan@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable MMU now is initialized in CpuDxe. There is no point to set satp to bare mode as that should be the default mode when booting edk2. Signed-off-by: Tuan Phan Reviewed-by: Andrei Warkentin --- OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc | 1 + OvmfPkg/RiscVVirt/Sec/Memory.c | 18 ++---------------- 2 files changed, 3 insertions(+), 16 deletions(-) diff --git a/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc b/OvmfPkg/RiscVVirt/RiscVV= irt.dsc.inc index 731f54f73f81..bc204ba5fe52 100644 --- a/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc +++ b/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc @@ -83,6 +83,7 @@ # RISC-V Architectural Libraries=0D CpuExceptionHandlerLib|UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandler= Lib/BaseRiscV64CpuExceptionHandlerLib.inf=0D RiscVSbiLib|MdePkg/Library/BaseRiscVSbiLib/BaseRiscVSbiLib.inf=0D + RiscVMmuLib|UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf=0D PlatformBootManagerLib|OvmfPkg/RiscVVirt/Library/PlatformBootManagerLib/= PlatformBootManagerLib.inf=0D ResetSystemLib|OvmfPkg/RiscVVirt/Library/ResetSystemLib/BaseResetSystemL= ib.inf=0D =0D diff --git a/OvmfPkg/RiscVVirt/Sec/Memory.c b/OvmfPkg/RiscVVirt/Sec/Memory.c index 0e2690c73687..aad71ee5dcbb 100644 --- a/OvmfPkg/RiscVVirt/Sec/Memory.c +++ b/OvmfPkg/RiscVVirt/Sec/Memory.c @@ -85,21 +85,6 @@ AddMemoryRangeHob ( AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));=0D }=0D =0D -/**=0D - Configure MMU=0D -**/=0D -STATIC=0D -VOID=0D -InitMmu (=0D - )=0D -{=0D - //=0D - // Set supervisor translation mode to Bare mode=0D - //=0D - RiscVSetSupervisorAddressTranslationRegister ((UINT64)SATP_MODE_OFF << 6= 0);=0D - DEBUG ((DEBUG_INFO, "%a: Set Supervisor address mode to bare-metal mode.= \n", __func__));=0D -}=0D -=0D /**=0D Publish system RAM and reserve memory regions.=0D =0D @@ -327,7 +312,8 @@ MemoryPeimInitialization ( =0D AddReservedMemoryMap (FdtPointer);=0D =0D - InitMmu ();=0D + /* Make sure SEC is booting with bare mode */=0D + ASSERT ((RiscVGetSupervisorAddressTranslationRegister () & SATP64_MODE) = =3D=3D (SATP_MODE_OFF << SATP64_MODE_SHIFT));=0D =0D BuildMemoryTypeInformationHob ();=0D =0D --=20 2.25.1