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[174.50.177.95]) by smtp.gmail.com with ESMTPSA id h20-20020a17090acf1400b00250ad795d72sm3223226pju.44.2023.05.26.16.25.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 May 2023 16:25:25 -0700 (PDT) From: "Tuan Phan" To: devel@edk2.groups.io Cc: eric.dong@intel.com, ray.ni@intel.com, rahul1.kumar@intel.com, git@danielschaefer.me, abner.chang@amd.com, kraxel@redhat.com, andrei.warkentin@intel.com, sunilvl@ventanamicro.com, Tuan Phan Subject: [PATCH 1/2] UefiCpuPkg: CpuTimerDxeRiscV64: Fix incorrect value sent to SbiSetTimer Date: Fri, 26 May 2023 16:25:17 -0700 Message-Id: <20230526232518.7141-1-tphan@ventanamicro.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable SbiSetTimer expects core tick value. Signed-off-by: Tuan Phan --- .../CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf | 3 +++ UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c | 26 ++++++++++++++++--- UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h | 2 +- 3 files changed, 26 insertions(+), 5 deletions(-) diff --git a/UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf b/UefiCpu= Pkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf index c76bd9648373..cd58d3a2f86b 100644 --- a/UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf +++ b/UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf @@ -40,6 +40,9 @@ Timer.h=0D Timer.c=0D =0D +[Pcd] + gUefiCpuPkgTokenSpaceGuid.PcdCpuCoreCrystalClockFrequency ## CONSUMES + [Protocols]=0D gEfiCpuArchProtocolGuid ## CONSUMES=0D gEfiTimerArchProtocolGuid ## PRODUCES=0D diff --git a/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c b/UefiCpuPkg/CpuTimerDxe= RiscV64/Timer.c index fa957ba5e3e9..a8afb649149f 100644 --- a/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c +++ b/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c @@ -80,8 +80,15 @@ TimerInterruptHandler ( return;=0D }=0D =0D - mLastPeriodStart =3D PeriodStart;=0D - SbiSetTimer (PeriodStart +=3D mTimerPeriod);=0D + mLastPeriodStart =3D PeriodStart;=0D + PeriodStart +=3D DivU64x32 (=0D + MultU64x32 (=0D + mTimerPeriod,=0D + PcdGet64 (PcdCpuCoreCrystalClockFrequency)=0D + ),=0D + 1000000u=0D + ); // convert to tick=0D + SbiSetTimer (PeriodStart);=0D RiscVEnableTimerInterrupt (); // enable SMode timer int=0D gBS->RestoreTPL (OriginalTPL);=0D }=0D @@ -163,6 +170,8 @@ TimerDriverSetTimerPeriod ( IN UINT64 TimerPeriod=0D )=0D {=0D + UINT64 PeriodStart;=0D +=0D DEBUG ((DEBUG_INFO, "TimerDriverSetTimerPeriod(0x%lx)\n", TimerPeriod));= =0D =0D if (TimerPeriod =3D=3D 0) {=0D @@ -171,9 +180,18 @@ TimerDriverSetTimerPeriod ( return EFI_SUCCESS;=0D }=0D =0D - mTimerPeriod =3D TimerPeriod / 10; // convert unit from 100ns to 1us= =0D + mTimerPeriod =3D TimerPeriod / 10; // convert unit from 100ns to 1us= =0D +=0D mLastPeriodStart =3D RiscVReadTimer ();=0D - SbiSetTimer (mLastPeriodStart + mTimerPeriod);=0D + PeriodStart =3D mLastPeriodStart;=0D + PeriodStart +=3D DivU64x32 (=0D + MultU64x32 (=0D + mTimerPeriod,=0D + PcdGet64 (PcdCpuCoreCrystalClockFrequency)=0D + ),=0D + 1000000u=0D + ); // convert to tick=0D + SbiSetTimer (PeriodStart);=0D =0D mCpu->EnableInterrupt (mCpu);=0D RiscVEnableTimerInterrupt (); // enable SMode timer int=0D diff --git a/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h b/UefiCpuPkg/CpuTimerDxe= RiscV64/Timer.h index 586eb0cfadb4..9b3542230cb5 100644 --- a/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h +++ b/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h @@ -21,7 +21,7 @@ #include =0D =0D //=0D -// RISC-V use 100us timer.=0D +// RISC-V use 100ns timer.=0D // The default timer tick duration is set to 10 ms =3D 10 * 1000 * 10 100 = ns units=0D //=0D #define DEFAULT_TIMER_TICK_DURATION 100000=0D --=20 2.25.1