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[174.50.177.95]) by smtp.gmail.com with ESMTPSA id h20-20020a17090acf1400b00250ad795d72sm3223226pju.44.2023.05.26.16.25.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 May 2023 16:25:26 -0700 (PDT) From: "Tuan Phan" To: devel@edk2.groups.io Cc: eric.dong@intel.com, ray.ni@intel.com, rahul1.kumar@intel.com, git@danielschaefer.me, abner.chang@amd.com, kraxel@redhat.com, andrei.warkentin@intel.com, sunilvl@ventanamicro.com, Tuan Phan Subject: [PATCH 2/2] UefiCpuPkg: RISC-V: TimerLib: Fix delay function to use 64-bit Date: Fri, 26 May 2023 16:25:18 -0700 Message-Id: <20230526232518.7141-2-tphan@ventanamicro.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230526232518.7141-1-tphan@ventanamicro.com> References: <20230526232518.7141-1-tphan@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable The timer compare register is 64-bit so simplifying the delay function. Signed-off-by: Tuan Phan --- MdePkg/Include/Register/RiscV64/RiscVImpl.h | 1 - .../BaseRiscV64CpuTimerLib/CpuTimerLib.c | 62 +++++++++---------- 2 files changed, 28 insertions(+), 35 deletions(-) diff --git a/MdePkg/Include/Register/RiscV64/RiscVImpl.h b/MdePkg/Include/R= egister/RiscV64/RiscVImpl.h index ee5c2ba60377..6997de6cc001 100644 --- a/MdePkg/Include/Register/RiscV64/RiscVImpl.h +++ b/MdePkg/Include/Register/RiscV64/RiscVImpl.h @@ -20,6 +20,5 @@ Name:=0D =0D #define ASM_FUNC(Name) _ASM_FUNC(ASM_PFX(Name), .text. ## Name)=0D -#define RISCV_TIMER_COMPARE_BITS 32=0D =0D #endif=0D diff --git a/UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/CpuTimerLib.c b/Uefi= CpuPkg/Library/BaseRiscV64CpuTimerLib/CpuTimerLib.c index 9c8efc0f3530..57800177023c 100644 --- a/UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/CpuTimerLib.c +++ b/UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/CpuTimerLib.c @@ -22,26 +22,19 @@ @param Delay A period of time to delay in ticks.=0D =0D **/=0D +STATIC=0D VOID=0D InternalRiscVTimerDelay (=0D - IN UINT32 Delay=0D + IN UINT64 Delay=0D )=0D {=0D - UINT32 Ticks;=0D - UINT32 Times;=0D -=0D - Times =3D Delay >> (RISCV_TIMER_COMPARE_BITS - 2);=0D - Delay &=3D ((1 << (RISCV_TIMER_COMPARE_BITS - 2)) - 1);=0D - do {=0D - //=0D - // The target timer count is calculated here=0D - //=0D - Ticks =3D RiscVReadTimer () + Delay;=0D - Delay =3D 1 << (RISCV_TIMER_COMPARE_BITS - 2);=0D - while (((Ticks - RiscVReadTimer ()) & (1 << (RISCV_TIMER_COMPARE_BITS = - 1))) =3D=3D 0) {=0D - CpuPause ();=0D - }=0D - } while (Times-- > 0);=0D + UINT64 Ticks;=0D +=0D + Ticks =3D RiscVReadTimer () + Delay;=0D +=0D + while (RiscVReadTimer () <=3D Ticks) {=0D + CpuPause ();=0D + }=0D }=0D =0D /**=0D @@ -61,14 +54,14 @@ MicroSecondDelay ( )=0D {=0D InternalRiscVTimerDelay (=0D - (UINT32)DivU64x32 (=0D - MultU64x32 (=0D - MicroSeconds,=0D - PcdGet64 (PcdCpuCoreCrystalClockFrequency)=0D - ),=0D - 1000000u=0D - )=0D - );=0D + DivU64x32 (=0D + MultU64x32 (=0D + MicroSeconds,=0D + PcdGet64 (PcdCpuCoreCrystalClockFrequency)=0D + ),=0D + 1000000u=0D + )=0D + );=0D return MicroSeconds;=0D }=0D =0D @@ -89,14 +82,14 @@ NanoSecondDelay ( )=0D {=0D InternalRiscVTimerDelay (=0D - (UINT32)DivU64x32 (=0D - MultU64x32 (=0D - NanoSeconds,=0D - PcdGet64 (PcdCpuCoreCrystalClockFrequency)=0D - ),=0D - 1000000000u=0D - )=0D - );=0D + DivU64x32 (=0D + MultU64x32 (=0D + NanoSeconds,=0D + PcdGet64 (PcdCpuCoreCrystalClockFrequency)=0D + ),=0D + 1000000000u=0D + )=0D + );=0D return NanoSeconds;=0D }=0D =0D @@ -147,8 +140,9 @@ GetPerformanceCounter ( UINT64=0D EFIAPI=0D GetPerformanceCounterProperties (=0D - OUT UINT64 *StartValue, OPTIONAL=0D - OUT UINT64 *EndValue OPTIONAL=0D + OUT UINT64 *StartValue,=0D + OPTIONAL=0D + OUT UINT64 *EndValue OPTIONAL=0D )=0D {=0D if (StartValue !=3D NULL) {=0D --=20 2.25.1