From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mx.groups.io with SMTP id smtpd.web10.5150.1685435435143085491 for ; Tue, 30 May 2023 01:30:35 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=KNpsqw+X; spf=pass (domain: intel.com, ip: 134.134.136.20, mailfrom: ray.ni@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1685435435; x=1716971435; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=rX4abBExHuSfNhfUdQjXhY75yhKHXdpPbmf4bN+cwkY=; b=KNpsqw+Xy+pPsYXXGyojiXGtCWRmc19cymweLB75gnoexyZCMgHCvEb9 +IfpUIxIsjMZ5FLmuJ7vX0OXf9ay1TrgIbabXN30GJG4IdQDGLn1VapXU nYNtd+Dy7oBGYJbuvEVEd7wXRItxxQ60KXqisHAk96hV/gb/G9qSyxwBC igCq3v73WXDhIGJy35Jo+pzEMx1mWRZEeM5zgkOMx6KdkEU4ufmNiM3u3 ITsbC40OkSnj+nKmrxdLOZM+Swn2SEEwHeKiPMIJQH4QN1Dhw1btnqhFA tlKpxagb52Rbwbgh4nlcRvhr+TGzo6jMUEx7E/Cr/fJlRrzGLptkRvso0 Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10725"; a="344353786" X-IronPort-AV: E=Sophos;i="6.00,203,1681196400"; d="scan'208";a="344353786" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 May 2023 01:30:34 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10725"; a="880682786" X-IronPort-AV: E=Sophos;i="6.00,203,1681196400"; d="scan'208";a="880682786" Received: from ray-dev.ccr.corp.intel.com ([10.239.158.139]) by orsmga005.jf.intel.com with ESMTP; 30 May 2023 01:30:33 -0700 From: "Ni, Ray" To: devel@edk2.groups.io Cc: Nate DeSimone , Zhiguang Liu Subject: [PATCH] SimicsOpenBoard: Use default 10ms as delay between INIT and SIPI Date: Tue, 30 May 2023 16:30:36 +0800 Message-Id: <20230530083036.696-1-ray.ni@intel.com> X-Mailer: git-send-email 2.37.2.windows.2 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Today the delay is 10us but the QSP simulates the multiprocessor by dividing time into segments and serializing processors within a segment. The length of the segment is configurable and Simics open board is configured using 100us. But the firmware configures the delay between INIT and SIPI is 10us. That results a possible senarino that BSP sends a INIT and SIPI in one segment (100us) while APs are still in SMM environment. The INIT is queued but SIPI is ignored by Simics, resulting all APs being put in wait-for-SIPI state when they receive INIT. Signed-off-by: Ray Ni Cc: Nate DeSimone Cc: Zhiguang Liu --- .../Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgPcd.dsc | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgPc= d.dsc b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgPcd.dsc index 732d95e44f..06c479b619 100644 --- a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgPcd.dsc +++ b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgPcd.dsc @@ -1,7 +1,7 @@ ## @file=0D # PCD configuration build description file for the X58Ich10 board.=0D #=0D -# Copyright (c) 2019 - 2022, Intel Corporation. All rights reserved.
= =0D +# Copyright (c) 2019 - 2023, Intel Corporation. All rights reserved.
= =0D #=0D # SPDX-License-Identifier: BSD-2-Clause-Patent=0D #=0D @@ -148,7 +148,6 @@ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddressMask|0xFFFC=0D gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiPm1TmrOffset|0x0008=0D gUefiCpuPkgTokenSpaceGuid.PcdCpuApStackSize|0x1000=0D - gUefiCpuPkgTokenSpaceGuid.PcdCpuInitIpiDelayInMicroSeconds|10=0D gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|512=0D gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|10000=0D gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize|0x4000=0D --=20 2.37.2.windows.2