From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by mx.groups.io with SMTP id smtpd.web11.11830.1685532887032383064 for ; Wed, 31 May 2023 04:34:49 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=cntUCVg8; spf=pass (domain: intel.com, ip: 192.55.52.136, mailfrom: ray.ni@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1685532889; x=1717068889; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=VowYGX1K9Y82tz1T5YShEVT1J0Hdx/gLrH+xrpJEI/0=; b=cntUCVg8KeKuutOK72p4YUzlT5Q98xGfgHNKNR0rY2+cNXQ5wmnltE0D 25q8BKJqjGQ83JE5+VBZkkPoVKtoQK02d8SDY1ZRCutGgQCq9Sx5l4P/C viRmZEAylzzYahNt4EVSdqcp8VMT/UWEGXofX47ozqOrWesY9xmicNrCb wuldDcLyVIkQR4FcBgkDJ2kgur3Uf1gUTxdde5GZ20a7h7Ao/QJjDtoHa VAJ20jnjA3f4zY1cQE8/b18qF1hFhvu5cwOfbLsYt4W51hwS9T1ns/Vq1 CxPR4/j01p7uceLc1OmP7/rNEOO7QUn8Ub4ttZHz1TJEHKbKxgRJ6Lupk w==; X-IronPort-AV: E=McAfee;i="6600,9927,10726"; a="334830242" X-IronPort-AV: E=Sophos;i="6.00,207,1681196400"; d="scan'208";a="334830242" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 May 2023 04:34:49 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10726"; a="739921480" X-IronPort-AV: E=Sophos;i="6.00,207,1681196400"; d="scan'208";a="739921480" Received: from shwdeopenlab706.ccr.corp.intel.com ([10.239.55.95]) by orsmga001.jf.intel.com with ESMTP; 31 May 2023 04:34:47 -0700 From: "Ni, Ray" To: devel@edk2.groups.io Cc: Eric Dong , Rahul Kumar , Gerd Hoffmann , Jiaxin Wu Subject: [PATCH V2 2/6] UefiCpuPkg/CpuSmm: Add perf-logging for MP procedures Date: Wed, 31 May 2023 19:34:34 +0800 Message-Id: <20230531113438.1797-3-ray.ni@intel.com> X-Mailer: git-send-email 2.39.1.windows.1 In-Reply-To: <20230531113438.1797-1-ray.ni@intel.com> References: <20230531113438.1797-1-ray.ni@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable MP procedures are those procedures that run in every CPU thread. The EDKII perf infra is not MP safe so it doesn't support to be called from those MP procedures. The patch adds SMM MP perf-logging support in SmmMpPerf.c. The following procedures are perf-logged: * SmmInitHandler * SmmCpuFeaturesRendezvousEntry * PlatformValidSmi * SmmCpuFeaturesRendezvousExit Cc: Eric Dong Cc: Rahul Kumar Cc: Gerd Hoffmann Cc: Jiaxin Wu --- UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c | 34 ++++++++ UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c | 11 +++ UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 1 + UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf | 2 + UefiCpuPkg/PiSmmCpuDxeSmm/SmmMpPerf.c | 91 ++++++++++++++++++++ UefiCpuPkg/PiSmmCpuDxeSmm/SmmMpPerf.h | 77 +++++++++++++++++ 6 files changed, 216 insertions(+) create mode 100644 UefiCpuPkg/PiSmmCpuDxeSmm/SmmMpPerf.c create mode 100644 UefiCpuPkg/PiSmmCpuDxeSmm/SmmMpPerf.h diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c b/UefiCpuPkg/PiSmmCpuDxe= Smm/MpService.c index fa666bd118..bcd90f0671 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c @@ -778,6 +778,15 @@ BSPHandler ( //=0D WaitForAllAPs (ApCount);=0D =0D + //=0D + // At this point, all APs should have exited from APHandler().=0D + // Migrate the SMM MP performance logging to standard SMM performance lo= gging.=0D + // Any SMM MP performance logging after this point will be migrated in n= ext SMI.=0D + //=0D + PERF_CODE (=0D + MigrateMpPerf (gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus);=0D + );=0D +=0D //=0D // Reset the tokens buffer.=0D //=0D @@ -1769,12 +1778,24 @@ SmiRendezvous ( //=0D // Perform CPU specific entry hooks=0D //=0D + PERF_CODE (=0D + MpPerfBegin (CpuIndex, SMM_MP_PERF_PROCEDURE_ID (SmmRendezvousEntry));= =0D + );=0D SmmCpuFeaturesRendezvousEntry (CpuIndex);=0D + PERF_CODE (=0D + MpPerfEnd (CpuIndex, SMM_MP_PERF_PROCEDURE_ID (SmmRendezvousEntry));=0D + );=0D =0D //=0D // Determine if this is a valid SMI=0D //=0D + PERF_CODE (=0D + MpPerfBegin (CpuIndex, SMM_MP_PERF_PROCEDURE_ID (PlatformValidSmi));=0D + );=0D ValidSmi =3D PlatformValidSmi ();=0D + PERF_CODE (=0D + MpPerfEnd (CpuIndex, SMM_MP_PERF_PROCEDURE_ID (PlatformValidSmi));=0D + );=0D =0D //=0D // Determine if BSP has been already in progress. Note this must be chec= ked after=0D @@ -1904,7 +1925,20 @@ SmiRendezvous ( }=0D =0D Exit:=0D + //=0D + // Note: SmmRendezvousExit perf-logging entry is the only one that will = be=0D + // migrated to standard perf-logging database in next SMI by BSPHa= ndler().=0D + // Hence, the number of SmmRendezvousEntry entries will be larger = than=0D + // the number of SmmRendezvousExit entries. Delta equals to the nu= mber=0D + // of CPU threads.=0D + //=0D + PERF_CODE (=0D + MpPerfBegin (CpuIndex, SMM_MP_PERF_PROCEDURE_ID (SmmRendezvousExit));= =0D + );=0D SmmCpuFeaturesRendezvousExit (CpuIndex);=0D + PERF_CODE (=0D + MpPerfEnd (CpuIndex, SMM_MP_PERF_PROCEDURE_ID (SmmRendezvousExit));=0D + );=0D =0D //=0D // Restore Cr2=0D diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c b/UefiCpuPkg/PiSmmC= puDxeSmm/PiSmmCpuDxeSmm.c index 2fc7dda682..5afab1e040 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c @@ -362,6 +362,9 @@ SmmInitHandler ( =0D for (Index =3D 0; Index < mNumberOfCpus; Index++) {=0D if (ApicId =3D=3D (UINT32)gSmmCpuPrivate->ProcessorInfo[Index].Process= orId) {=0D + PERF_CODE (=0D + MpPerfBegin (Index, SMM_MP_PERF_PROCEDURE_ID (SmmInitHandler));=0D + );=0D //=0D // Initialize SMM specific features on the currently executing CPU=0D //=0D @@ -392,6 +395,10 @@ SmmInitHandler ( SemaphoreHook (Index, &mRebased[Index]);=0D }=0D =0D + PERF_CODE (=0D + MpPerfEnd (Index, SMM_MP_PERF_PROCEDURE_ID (SmmInitHandler));=0D + );=0D +=0D return;=0D }=0D }=0D @@ -699,6 +706,10 @@ PiCpuSmmEntry ( =0D gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus =3D mMaxNumberOfCpus;=0D =0D + PERF_CODE (=0D + InitializeMpPerf (gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus);=0D + );=0D +=0D //=0D // The CPU save state and code for the SMI entry point are tiled within = an SMRAM=0D // allocated buffer. The minimum size of this buffer for a uniprocessor= system=0D diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h b/UefiCpuPkg/PiSmmC= puDxeSmm/PiSmmCpuDxeSmm.h index b03f2ef882..1876a27cae 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h @@ -60,6 +60,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent =0D #include "CpuService.h"=0D #include "SmmProfile.h"=0D +#include "SmmMpPerf.h"=0D =0D //=0D // CET definition=0D diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf b/UefiCpuPkg/PiSm= mCpuDxeSmm/PiSmmCpuDxeSmm.inf index af66a1941c..4864532c35 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf @@ -42,6 +42,8 @@ SmmCpuMemoryManagement.c=0D SmmMp.h=0D SmmMp.c=0D + SmmMpPerf.h=0D + SmmMpPerf.c=0D =0D [Sources.Ia32]=0D Ia32/Semaphore.c=0D diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmMpPerf.c b/UefiCpuPkg/PiSmmCpuDxe= Smm/SmmMpPerf.c new file mode 100644 index 0000000000..c13556af46 --- /dev/null +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmMpPerf.c @@ -0,0 +1,91 @@ +/** @file=0D +SMM MP perf-logging implementation=0D +=0D +Copyright (c) 2023, Intel Corporation. All rights reserved.
=0D +=0D +SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#include "PiSmmCpuDxeSmm.h"=0D +=0D +=0D +#define SMM_MP_PERF_PROCEDURE_NAME(procedure) # procedure=0D +GLOBAL_REMOVE_IF_UNREFERENCED=0D +CHAR8 *gSmmMpPerfProcedureName[] =3D {=0D + SMM_MP_PERF_PROCEDURE_LIST (SMM_MP_PERF_PROCEDURE_NAME)=0D +};=0D +//=0D +// Each element holds the performance data for one processor.=0D +//=0D +GLOBAL_REMOVE_IF_UNREFERENCED=0D +SMM_PERF_AP_PROCEDURE_PERFORMANCE *mSmmMpProcedurePerformance =3D NULL;=0D +=0D +/**=0D + Initialize the perf-logging feature for APs.=0D +=0D + @param NumberofCpus Number of processors in the platform.=0D +**/=0D +VOID=0D +InitializeMpPerf (=0D + UINTN NumberofCpus=0D + )=0D +{=0D + mSmmMpProcedurePerformance =3D AllocateZeroPool (NumberofCpus * sizeof (= *mSmmMpProcedurePerformance));=0D + ASSERT (mSmmMpProcedurePerformance !=3D NULL);=0D +}=0D +=0D +/**=0D + Migrate MP performance data to standardized performance database.=0D +=0D + @param NumberofCpus Number of processors in the platform.=0D +**/=0D +VOID=0D +MigrateMpPerf (=0D + UINTN NumberofCpus=0D + )=0D +{=0D + UINTN CpuIndex;=0D + UINTN MpProcecureId;=0D +=0D + for (CpuIndex =3D 0; CpuIndex < NumberofCpus; CpuIndex++) {=0D + for (MpProcecureId =3D 0; MpProcecureId < SMM_MP_PERF_PROCEDURE_ID (Sm= mMpProcedureMax); MpProcecureId++) {=0D + if (mSmmMpProcedurePerformance[CpuIndex].Begin[MpProcecureId] !=3D 0= ) {=0D + PERF_START (NULL, gSmmMpPerfProcedureName[MpProcecureId], NULL, mS= mmMpProcedurePerformance[CpuIndex].Begin[MpProcecureId]);=0D + PERF_END (NULL, gSmmMpPerfProcedureName[MpProcecureId], NULL, mSmm= MpProcedurePerformance[CpuIndex].End[MpProcecureId]);=0D + }=0D + }=0D + }=0D +=0D + ZeroMem (mSmmMpProcedurePerformance, NumberofCpus * sizeof (*mSmmMpProce= durePerformance));=0D +}=0D +=0D +/**=0D + Save the performance counter value before running the MP procedure.=0D +=0D + @param CpuIndex The index of the CPU.=0D + @param MpProcedureId The ID of the MP procedure.=0D +**/=0D +VOID=0D +MpPerfBegin (=0D + IN UINTN CpuIndex,=0D + IN UINTN MpProcedureId=0D + )=0D +{=0D + mSmmMpProcedurePerformance[CpuIndex].Begin[MpProcedureId] =3D GetPerform= anceCounter ();=0D +}=0D +=0D +/**=0D + Save the performance counter value after running the MP procedure.=0D +=0D + @param CpuIndex The index of the CPU.=0D + @param MpProcedureId The ID of the MP procedure.=0D +**/=0D +VOID=0D +MpPerfEnd (=0D + IN UINTN CpuIndex,=0D + IN UINTN MpProcedureId=0D + )=0D +{=0D + mSmmMpProcedurePerformance[CpuIndex].End[MpProcedureId] =3D GetPerforman= ceCounter ();=0D +}=0D diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmMpPerf.h b/UefiCpuPkg/PiSmmCpuDxe= Smm/SmmMpPerf.h new file mode 100644 index 0000000000..b148a99e86 --- /dev/null +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmMpPerf.h @@ -0,0 +1,77 @@ +/** @file=0D +SMM MP perf-logging implementation=0D +=0D +Copyright (c) 2023, Intel Corporation. All rights reserved.
=0D +=0D +SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#ifndef _MP_PERF_H_=0D +#define _MP_PERF_H_=0D +=0D +//=0D +// The list of all MP procedures that need to be perf-logged.=0D +//=0D +#define SMM_MP_PERF_PROCEDURE_LIST(_) \=0D + _(SmmInitHandler), \=0D + _(SmmRendezvousEntry), \=0D + _(PlatformValidSmi), \=0D + _(SmmRendezvousExit), \=0D + _(SmmMpProcedureMax) // Add new entries above this line=0D +=0D +#define SMM_MP_PERF_PROCEDURE_ID(procedure) SmmMpProcedureId ## procedur= e=0D +enum {=0D + SMM_MP_PERF_PROCEDURE_LIST (SMM_MP_PERF_PROCEDURE_ID)=0D +};=0D +=0D +typedef struct {=0D + UINT64 Begin[SMM_MP_PERF_PROCEDURE_ID (SmmMpProcedureMax)];=0D + UINT64 End[SMM_MP_PERF_PROCEDURE_ID (SmmMpProcedureMax)];=0D +} SMM_PERF_AP_PROCEDURE_PERFORMANCE;=0D +=0D +/**=0D + Initialize the perf-logging feature for APs.=0D +=0D + @param NumberofCpus Number of processors in the platform.=0D +**/=0D +VOID=0D +InitializeMpPerf (=0D + UINTN NumberofCpus=0D + );=0D +=0D +/**=0D + Migrate MP performance data to standardized performance database.=0D +=0D + @param NumberofCpus Number of processors in the platform.=0D +**/=0D +VOID=0D +MigrateMpPerf (=0D + UINTN NumberofCpus=0D + );=0D +=0D +/**=0D + Save the performance counter value before running the MP procedure.=0D +=0D + @param CpuIndex The index of the CPU.=0D + @param MpProcedureId The ID of the MP procedure.=0D +**/=0D +VOID=0D +MpPerfBegin (=0D + IN UINTN CpuIndex,=0D + IN UINTN MpProcedureId=0D + );=0D +=0D +/**=0D + Save the performance counter value after running the MP procedure.=0D +=0D + @param CpuIndex The index of the CPU.=0D + @param MpProcedureId The ID of the MP procedure.=0D +**/=0D +VOID=0D +MpPerfEnd (=0D + IN UINTN CpuIndex,=0D + IN UINTN MpProcedureId=0D + );=0D +=0D +#endif=0D --=20 2.39.1.windows.1