* [PATCH v2 1/2] UefiCpuPkg: CpuTimerDxeRiscV64: Fix incorrect value sent to SbiSetTimer
@ 2023-06-07 17:30 Tuan Phan
2023-06-07 17:30 ` [PATCH v2 2/2] UefiCpuPkg: RISC-V: TimerLib: Fix delay function to use 64-bit Tuan Phan
0 siblings, 1 reply; 2+ messages in thread
From: Tuan Phan @ 2023-06-07 17:30 UTC (permalink / raw)
To: devel; +Cc: eric.dong, ray.ni, andrei.warkentin, sunilvl, Tuan Phan
SbiSetTimer expects core tick value.
Cc: Andrei Warkentin <andrei.warkentin@intel.com>
Signed-off-by: Tuan Phan <tphan@ventanamicro.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
---
V2: Fixed format issue with uncrustify.
.../CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf | 3 +++
UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c | 26 ++++++++++++++++---
UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h | 2 +-
3 files changed, 26 insertions(+), 5 deletions(-)
diff --git a/UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf b/UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf
index c76bd9648373..aba660186dc0 100644
--- a/UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf
+++ b/UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf
@@ -40,6 +40,9 @@
Timer.h
Timer.c
+[Pcd]
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuCoreCrystalClockFrequency ## CONSUMES
+
[Protocols]
gEfiCpuArchProtocolGuid ## CONSUMES
gEfiTimerArchProtocolGuid ## PRODUCES
diff --git a/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c b/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c
index fa957ba5e3e9..358057e7c6a4 100644
--- a/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c
+++ b/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c
@@ -80,8 +80,15 @@ TimerInterruptHandler (
return;
}
- mLastPeriodStart = PeriodStart;
- SbiSetTimer (PeriodStart += mTimerPeriod);
+ mLastPeriodStart = PeriodStart;
+ PeriodStart += DivU64x32 (
+ MultU64x32 (
+ mTimerPeriod,
+ PcdGet64 (PcdCpuCoreCrystalClockFrequency)
+ ),
+ 1000000u
+ ); // convert to tick
+ SbiSetTimer (PeriodStart);
RiscVEnableTimerInterrupt (); // enable SMode timer int
gBS->RestoreTPL (OriginalTPL);
}
@@ -163,6 +170,8 @@ TimerDriverSetTimerPeriod (
IN UINT64 TimerPeriod
)
{
+ UINT64 PeriodStart;
+
DEBUG ((DEBUG_INFO, "TimerDriverSetTimerPeriod(0x%lx)\n", TimerPeriod));
if (TimerPeriod == 0) {
@@ -171,9 +180,18 @@ TimerDriverSetTimerPeriod (
return EFI_SUCCESS;
}
- mTimerPeriod = TimerPeriod / 10; // convert unit from 100ns to 1us
+ mTimerPeriod = TimerPeriod / 10; // convert unit from 100ns to 1us
+
mLastPeriodStart = RiscVReadTimer ();
- SbiSetTimer (mLastPeriodStart + mTimerPeriod);
+ PeriodStart = mLastPeriodStart;
+ PeriodStart += DivU64x32 (
+ MultU64x32 (
+ mTimerPeriod,
+ PcdGet64 (PcdCpuCoreCrystalClockFrequency)
+ ),
+ 1000000u
+ ); // convert to tick
+ SbiSetTimer (PeriodStart);
mCpu->EnableInterrupt (mCpu);
RiscVEnableTimerInterrupt (); // enable SMode timer int
diff --git a/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h b/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h
index 586eb0cfadb4..9b3542230cb5 100644
--- a/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h
+++ b/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h
@@ -21,7 +21,7 @@
#include <Library/IoLib.h>
//
-// RISC-V use 100us timer.
+// RISC-V use 100ns timer.
// The default timer tick duration is set to 10 ms = 10 * 1000 * 10 100 ns units
//
#define DEFAULT_TIMER_TICK_DURATION 100000
--
2.25.1
^ permalink raw reply related [flat|nested] 2+ messages in thread
* [PATCH v2 2/2] UefiCpuPkg: RISC-V: TimerLib: Fix delay function to use 64-bit
2023-06-07 17:30 [PATCH v2 1/2] UefiCpuPkg: CpuTimerDxeRiscV64: Fix incorrect value sent to SbiSetTimer Tuan Phan
@ 2023-06-07 17:30 ` Tuan Phan
0 siblings, 0 replies; 2+ messages in thread
From: Tuan Phan @ 2023-06-07 17:30 UTC (permalink / raw)
To: devel; +Cc: eric.dong, ray.ni, andrei.warkentin, sunilvl, Tuan Phan
The timer compare register is 64-bit so simplifying the delay
function.
Cc: Andrei Warkentin <andrei.warkentin@intel.com>
Signed-off-by: Tuan Phan <tphan@ventanamicro.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
---
V2: Fix format issue with uncrustify.
MdePkg/Include/Register/RiscV64/RiscVImpl.h | 1 -
.../BaseRiscV64CpuTimerLib/CpuTimerLib.c | 53 ++++++++-----------
2 files changed, 23 insertions(+), 31 deletions(-)
diff --git a/MdePkg/Include/Register/RiscV64/RiscVImpl.h b/MdePkg/Include/Register/RiscV64/RiscVImpl.h
index ee5c2ba60377..6997de6cc001 100644
--- a/MdePkg/Include/Register/RiscV64/RiscVImpl.h
+++ b/MdePkg/Include/Register/RiscV64/RiscVImpl.h
@@ -20,6 +20,5 @@
Name:
#define ASM_FUNC(Name) _ASM_FUNC(ASM_PFX(Name), .text. ## Name)
-#define RISCV_TIMER_COMPARE_BITS 32
#endif
diff --git a/UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/CpuTimerLib.c b/UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/CpuTimerLib.c
index 9c8efc0f3530..27d7276aaa8a 100644
--- a/UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/CpuTimerLib.c
+++ b/UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/CpuTimerLib.c
@@ -22,26 +22,19 @@
@param Delay A period of time to delay in ticks.
**/
+STATIC
VOID
InternalRiscVTimerDelay (
- IN UINT32 Delay
+ IN UINT64 Delay
)
{
- UINT32 Ticks;
- UINT32 Times;
-
- Times = Delay >> (RISCV_TIMER_COMPARE_BITS - 2);
- Delay &= ((1 << (RISCV_TIMER_COMPARE_BITS - 2)) - 1);
- do {
- //
- // The target timer count is calculated here
- //
- Ticks = RiscVReadTimer () + Delay;
- Delay = 1 << (RISCV_TIMER_COMPARE_BITS - 2);
- while (((Ticks - RiscVReadTimer ()) & (1 << (RISCV_TIMER_COMPARE_BITS - 1))) == 0) {
- CpuPause ();
- }
- } while (Times-- > 0);
+ UINT64 Ticks;
+
+ Ticks = RiscVReadTimer () + Delay;
+
+ while (RiscVReadTimer () <= Ticks) {
+ CpuPause ();
+ }
}
/**
@@ -61,13 +54,13 @@ MicroSecondDelay (
)
{
InternalRiscVTimerDelay (
- (UINT32)DivU64x32 (
- MultU64x32 (
- MicroSeconds,
- PcdGet64 (PcdCpuCoreCrystalClockFrequency)
- ),
- 1000000u
- )
+ DivU64x32 (
+ MultU64x32 (
+ MicroSeconds,
+ PcdGet64 (PcdCpuCoreCrystalClockFrequency)
+ ),
+ 1000000u
+ )
);
return MicroSeconds;
}
@@ -89,13 +82,13 @@ NanoSecondDelay (
)
{
InternalRiscVTimerDelay (
- (UINT32)DivU64x32 (
- MultU64x32 (
- NanoSeconds,
- PcdGet64 (PcdCpuCoreCrystalClockFrequency)
- ),
- 1000000000u
- )
+ DivU64x32 (
+ MultU64x32 (
+ NanoSeconds,
+ PcdGet64 (PcdCpuCoreCrystalClockFrequency)
+ ),
+ 1000000000u
+ )
);
return NanoSeconds;
}
--
2.25.1
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