From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by mx.groups.io with SMTP id smtpd.web11.379.1686191316401101708 for ; Wed, 07 Jun 2023 19:28:41 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=PvpZmSuj; spf=pass (domain: intel.com, ip: 192.55.52.115, mailfrom: dun.tan@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1686191321; x=1717727321; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=eTnWmYX31ThziW0F42PD0u1dyiTsoQSyR8yHrdMgwGY=; b=PvpZmSujGJGBOYLISmExkrBzMaeZfUvyBQt8JreB0wxN+tLUTReNXiUD MSFScn9xfe6LHoWEKkAQfJV7v6k3MSBNTBxNbwm9qWoReomqaeQtSYWQY wQxaboqbihevzMKI80SgNSYzYeyXIqB4OzgW9lzipkTZ4T7hV9/zxEI8o K/FADsmc5ynzu2L2N5n0aIcgzuD9VSP4/+q+Z7UMNXviQ5IfGM5qzFGjv 6MTkPrJa0sYRNqpdK2y3BxI0c21WHn7RXsDkwSED5qItda2oCc6RQItgL 2SEfIlY/ziTNvsqi1yCXjaelL21c+fCQNlAZfg7vtIukZn8mANTxUYUr3 g==; X-IronPort-AV: E=McAfee;i="6600,9927,10734"; a="357184266" X-IronPort-AV: E=Sophos;i="6.00,225,1681196400"; d="scan'208";a="357184266" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jun 2023 19:28:40 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10734"; a="774877780" X-IronPort-AV: E=Sophos;i="6.00,225,1681196400"; d="scan'208";a="774877780" Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.158]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jun 2023 19:28:39 -0700 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [Patch V5 06/14] UefiCpuPkg/PiSmmCpuDxeSmm: Add 2 function to disable/enable CR0.WP Date: Thu, 8 Jun 2023 10:27:34 +0800 Message-Id: <20230608022742.1292-7-dun.tan@intel.com> X-Mailer: git-send-email 2.31.1.windows.1 In-Reply-To: <20230608022742.1292-1-dun.tan@intel.com> References: <20230608022742.1292-1-dun.tan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add two functions to disable/enable CR0.WP. These two unctions will also be used in later commits. This commit doesn't change any functionality. Signed-off-by: Dun Tan Cc: Eric Dong Reviewed-by: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann --- UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 24 ++++++++++++++++++++++++ UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c | 115 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++------------------------------------------------- 2 files changed, 90 insertions(+), 49 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h index ba341cadc6..e0c4ca76dc 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h @@ -1565,4 +1565,28 @@ SmmWaitForApArrival ( VOID ); +/** + Disable Write Protect on pages marked as read-only if Cr0.Bits.WP is 1. + + @param[out] WpEnabled If Cr0.WP is enabled. + @param[out] CetEnabled If CET is enabled. +**/ +VOID +DisableReadOnlyPageWriteProtect ( + OUT BOOLEAN *WpEnabled, + OUT BOOLEAN *CetEnabled + ); + +/** + Enable Write Protect on pages marked as read-only. + + @param[out] WpEnabled If Cr0.WP should be enabled. + @param[out] CetEnabled If CET should be enabled. +**/ +VOID +EnableReadOnlyPageWriteProtect ( + BOOLEAN WpEnabled, + BOOLEAN CetEnabled + ); + #endif diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c index 3c79927c7b..d35058ed00 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c @@ -40,6 +40,64 @@ PAGE_TABLE_POOL *mPageTablePool = NULL; // BOOLEAN mIsReadOnlyPageTable = FALSE; +/** + Disable Write Protect on pages marked as read-only if Cr0.Bits.WP is 1. + + @param[out] WpEnabled If Cr0.WP is enabled. + @param[out] CetEnabled If CET is enabled. +**/ +VOID +DisableReadOnlyPageWriteProtect ( + OUT BOOLEAN *WpEnabled, + OUT BOOLEAN *CetEnabled + ) +{ + IA32_CR0 Cr0; + + *CetEnabled = ((AsmReadCr4 () & CR4_CET_ENABLE) != 0) ? TRUE : FALSE; + Cr0.UintN = AsmReadCr0 (); + *WpEnabled = (Cr0.Bits.WP != 0) ? TRUE : FALSE; + if (*WpEnabled) { + if (*CetEnabled) { + // + // CET must be disabled if WP is disabled. Disable CET before clearing CR0.WP. + // + DisableCet (); + } + + Cr0.Bits.WP = 0; + AsmWriteCr0 (Cr0.UintN); + } +} + +/** + Enable Write Protect on pages marked as read-only. + + @param[out] WpEnabled If Cr0.WP should be enabled. + @param[out] CetEnabled If CET should be enabled. +**/ +VOID +EnableReadOnlyPageWriteProtect ( + BOOLEAN WpEnabled, + BOOLEAN CetEnabled + ) +{ + IA32_CR0 Cr0; + + if (WpEnabled) { + Cr0.UintN = AsmReadCr0 (); + Cr0.Bits.WP = 1; + AsmWriteCr0 (Cr0.UintN); + + if (CetEnabled) { + // + // re-enable CET. + // + EnableCet (); + } + } +} + /** Initialize a buffer pool for page table use only. @@ -62,10 +120,9 @@ InitializePageTablePool ( IN UINTN PoolPages ) { - VOID *Buffer; - BOOLEAN CetEnabled; - BOOLEAN WpEnabled; - IA32_CR0 Cr0; + VOID *Buffer; + BOOLEAN WpEnabled; + BOOLEAN CetEnabled; // // Always reserve at least PAGE_TABLE_POOL_UNIT_PAGES, including one page for @@ -102,34 +159,9 @@ InitializePageTablePool ( // If page table memory has been marked as RO, mark the new pool pages as read-only. // if (mIsReadOnlyPageTable) { - CetEnabled = ((AsmReadCr4 () & CR4_CET_ENABLE) != 0) ? TRUE : FALSE; - Cr0.UintN = AsmReadCr0 (); - WpEnabled = (Cr0.Bits.WP != 0) ? TRUE : FALSE; - if (WpEnabled) { - if (CetEnabled) { - // - // CET must be disabled if WP is disabled. Disable CET before clearing CR0.WP. - // - DisableCet (); - } - - Cr0.Bits.WP = 0; - AsmWriteCr0 (Cr0.UintN); - } - + DisableReadOnlyPageWriteProtect (&WpEnabled, &CetEnabled); SmmSetMemoryAttributes ((EFI_PHYSICAL_ADDRESS)(UINTN)Buffer, EFI_PAGES_TO_SIZE (PoolPages), EFI_MEMORY_RO); - if (WpEnabled) { - Cr0.UintN = AsmReadCr0 (); - Cr0.Bits.WP = 1; - AsmWriteCr0 (Cr0.UintN); - - if (CetEnabled) { - // - // re-enable CET. - // - EnableCet (); - } - } + EnableReadOnlyPageWriteProtect (WpEnabled, CetEnabled); } return TRUE; @@ -1780,6 +1812,7 @@ SetPageTableAttributes ( VOID ) { + BOOLEAN WpEnabled; BOOLEAN CetEnabled; if (!IfReadOnlyPageTableNeeded ()) { @@ -1792,15 +1825,7 @@ SetPageTableAttributes ( // Disable write protection, because we need mark page table to be write protected. // We need *write* page table memory, to mark itself to be *read only*. // - CetEnabled = ((AsmReadCr4 () & CR4_CET_ENABLE) != 0) ? TRUE : FALSE; - if (CetEnabled) { - // - // CET must be disabled if WP is disabled. - // - DisableCet (); - } - - AsmWriteCr0 (AsmReadCr0 () & ~CR0_WP); + DisableReadOnlyPageWriteProtect (&WpEnabled, &CetEnabled); // Set memory used by page table as Read Only. DEBUG ((DEBUG_INFO, "Start...\n")); @@ -1809,20 +1834,12 @@ SetPageTableAttributes ( // // Enable write protection, after page table attribute updated. // - AsmWriteCr0 (AsmReadCr0 () | CR0_WP); + EnableReadOnlyPageWriteProtect (TRUE, CetEnabled); mIsReadOnlyPageTable = TRUE; // // Flush TLB after mark all page table pool as read only. // FlushTlbForAll (); - - if (CetEnabled) { - // - // re-enable CET. - // - EnableCet (); - } - return; } -- 2.31.1.windows.1