From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by mx.groups.io with SMTP id smtpd.web11.379.1686191316401101708 for ; Wed, 07 Jun 2023 19:28:44 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=K+5Yt+qb; spf=pass (domain: intel.com, ip: 192.55.52.115, mailfrom: dun.tan@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1686191324; x=1717727324; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=V5CahrVcIedMxNpcRYS8LSnRsZ5Iwm3hNtA3MZSZ9Jg=; b=K+5Yt+qbZsO063/x3CQ8KkayA0c1e4mdpWfuxmpW2Pzr41EsjuTxKKfA 01faqkqWKKUTCPSpIeMNahsYJPtGMvblEmCZpG4BkaqEXDnuPNjvd/+lU YK11YBzVoY1Xyb0tFHYFdd0Q4bMmDH5bRei4eVZCsYi0KkFowkJq6ThqV OAQdo/nhrrGVTAVxURKHPqpSk3q6PWjRR2kMXjBZW4LyE4IjGDuQUA+sq zpJDqAKvWMh+exDvquJQaaA+tbjn8078nuR3vIbsHdMQv4Po5k++ES1vA lzCR6iDRzI6QhTjIv9McFkO1RDAskiHTf6rVKC54Ub1szJZh3crw88JIU g==; X-IronPort-AV: E=McAfee;i="6600,9927,10734"; a="357184288" X-IronPort-AV: E=Sophos;i="6.00,225,1681196400"; d="scan'208";a="357184288" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jun 2023 19:28:44 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10734"; a="774877811" X-IronPort-AV: E=Sophos;i="6.00,225,1681196400"; d="scan'208";a="774877811" Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.158]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jun 2023 19:28:42 -0700 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [Patch V5 07/14] UefiCpuPkg/PiSmmCpuDxeSmm: Clear CR0.WP before modify page table Date: Thu, 8 Jun 2023 10:27:35 +0800 Message-Id: <20230608022742.1292-8-dun.tan@intel.com> X-Mailer: git-send-email 2.31.1.windows.1 In-Reply-To: <20230608022742.1292-1-dun.tan@intel.com> References: <20230608022742.1292-1-dun.tan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Clear CR0.WP before modify smm page table. Currently, there is an assumption that smm pagetable is always RW before ReadyToLock. However, when AMD SEV is enabled, FvbServicesSmm driver calls MemEncryptSevClearMmioPageEncMask to clear AddressEncMask bit in smm page table for this range: [PcdOvmfFdBaseAddress,PcdOvmfFdBaseAddress+PcdOvmfFirmwareFdSize] If page slpit happens in this process, new memory for smm page table is allocated. Then the newly allocated page table memory is marked as RO in smm page table in this FvbServicesSmm driver, which may lead to PF if smm code doesn't clear CR0.WP before modify smm page table when ReadyToLock. Signed-off-by: Dun Tan Cc: Eric Dong Reviewed-by: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann --- UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c | 11 +++++++++++ UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c | 5 +++++ 2 files changed, 16 insertions(+) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c index d35058ed00..4ee99d06d7 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c @@ -1033,6 +1033,8 @@ SetMemMapAttributes ( IA32_MAP_ENTRY *Map; UINTN Count; UINT64 MemoryAttribute; + BOOLEAN WpEnabled; + BOOLEAN CetEnabled; SmmGetSystemConfigurationTable (&gEdkiiPiSmmMemoryAttributesTableGuid, (VOID **)&MemoryAttributesTable); if (MemoryAttributesTable == NULL) { @@ -1075,6 +1077,8 @@ SetMemMapAttributes ( ASSERT_RETURN_ERROR (Status); + DisableReadOnlyPageWriteProtect (&WpEnabled, &CetEnabled); + MemoryMap = MemoryMapStart; for (Index = 0; Index < MemoryMapEntryCount; Index++) { DEBUG ((DEBUG_VERBOSE, "SetAttribute: Memory Entry - 0x%lx, 0x%x\n", MemoryMap->PhysicalStart, MemoryMap->NumberOfPages)); @@ -1103,6 +1107,7 @@ SetMemMapAttributes ( MemoryMap = NEXT_MEMORY_DESCRIPTOR (MemoryMap, DescriptorSize); } + EnableReadOnlyPageWriteProtect (WpEnabled, CetEnabled); FreePool (Map); PatchSmmSaveStateMap (); @@ -1409,9 +1414,13 @@ SetUefiMemMapAttributes ( UINTN MemoryMapEntryCount; UINTN Index; EFI_MEMORY_DESCRIPTOR *Entry; + BOOLEAN WpEnabled; + BOOLEAN CetEnabled; DEBUG ((DEBUG_INFO, "SetUefiMemMapAttributes\n")); + DisableReadOnlyPageWriteProtect (&WpEnabled, &CetEnabled); + if (mUefiMemoryMap != NULL) { MemoryMapEntryCount = mUefiMemoryMapSize/mUefiDescriptorSize; MemoryMap = mUefiMemoryMap; @@ -1490,6 +1499,8 @@ SetUefiMemMapAttributes ( } } + EnableReadOnlyPageWriteProtect (WpEnabled, CetEnabled); + // // Do not free mUefiMemoryAttributesTable, it will be checked in IsSmmCommBufferForbiddenAddress(). // diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c index 1b0b6673e1..5625ba0cac 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c @@ -574,6 +574,8 @@ InitPaging ( BOOLEAN Nx; IA32_CR4 Cr4; BOOLEAN Enable5LevelPaging; + BOOLEAN WpEnabled; + BOOLEAN CetEnabled; Cr4.UintN = AsmReadCr4 (); Enable5LevelPaging = (BOOLEAN)(Cr4.Bits.LA57 == 1); @@ -620,6 +622,7 @@ InitPaging ( NumberOfPdptEntries = 4; } + DisableReadOnlyPageWriteProtect (&WpEnabled, &CetEnabled); // // Go through page table and change 2MB-page into 4KB-page. // @@ -800,6 +803,8 @@ InitPaging ( } // end for PML4 } // end for PML5 + EnableReadOnlyPageWriteProtect (WpEnabled, CetEnabled); + // // Flush TLB // -- 2.31.1.windows.1