From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by mx.groups.io with SMTP id smtpd.web11.379.1686191316401101708 for ; Wed, 07 Jun 2023 19:28:48 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=OMkRePef; spf=pass (domain: intel.com, ip: 192.55.52.115, mailfrom: dun.tan@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1686191327; x=1717727327; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ob2gxPTRfsC8O6S5oDIu36lDHguC2vBkL2TYEkdsb28=; b=OMkRePefVdHOcrUrcoI4UhH4gozu7/xaZmo/jOq4NhsWZgu1B0aNtbbM lCRt+zxwpS50PxOIDLmfaCMvTXfiKKL6+COMMz128cW973elkkdTiicRy TSw+wKiVk5CCb27lempDbDaiqSrWE8Qh6Enos4FhrWgTzUcAwl3eAhx31 aCNENpfJWCZDsYq3XpdPWDQH7+TpTRmp6eLMaVYp1fLGsV6Wdh6U4OQ0V VoMc7Epyajk6480LFW3Pb3TuoRYRF4L1sViNcTRt53csBzY8AAgPF5QLh lDnwK2OJXO04R3/N46uNFNBYGW0IuHa9jLpd4cXGe5oR/x9/hOBpdJsrn A==; X-IronPort-AV: E=McAfee;i="6600,9927,10734"; a="357184302" X-IronPort-AV: E=Sophos;i="6.00,225,1681196400"; d="scan'208";a="357184302" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jun 2023 19:28:47 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10734"; a="774877832" X-IronPort-AV: E=Sophos;i="6.00,225,1681196400"; d="scan'208";a="774877832" Received: from shwdeopenlab702.ccr.corp.intel.com ([10.239.55.158]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jun 2023 19:28:46 -0700 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [Patch V5 08/14] UefiCpuPkg: Extern mSmmShadowStackSize in PiSmmCpuDxeSmm.h Date: Thu, 8 Jun 2023 10:27:36 +0800 Message-Id: <20230608022742.1292-9-dun.tan@intel.com> X-Mailer: git-send-email 2.31.1.windows.1 In-Reply-To: <20230608022742.1292-1-dun.tan@intel.com> References: <20230608022742.1292-1-dun.tan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Extern mSmmShadowStackSize in PiSmmCpuDxeSmm.h and remove extern for mSmmShadowStackSize in c files to simplify code. Signed-off-by: Dun Tan Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann --- UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmFuncsArch.c | 3 +-- UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c | 2 -- UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 1 + UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c | 2 -- UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c | 3 +-- 5 files changed, 3 insertions(+), 8 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmFuncsArch.c b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmFuncsArch.c index 6c48a53f67..636dc8d92f 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmFuncsArch.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmFuncsArch.c @@ -1,7 +1,7 @@ /** @file SMM CPU misc functions for Ia32 arch specific. -Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.
+Copyright (c) 2015 - 2023, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -14,7 +14,6 @@ EFI_PHYSICAL_ADDRESS mGdtBuffer; UINTN mGdtBufferSize; extern BOOLEAN mCetSupported; -extern UINTN mSmmShadowStackSize; X86_ASSEMBLY_PATCH_LABEL mPatchCetPl0Ssp; X86_ASSEMBLY_PATCH_LABEL mPatchCetInterruptSsp; diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c index baf827cf9d..1878252eac 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c @@ -29,8 +29,6 @@ MM_COMPLETION mSmmStartupThisApToken; // UINT32 *mPackageFirstThreadIndex = NULL; -extern UINTN mSmmShadowStackSize; - /** Performs an atomic compare exchange operation to get semaphore. The compare exchange operation must be performed using diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h index e0c4ca76dc..a7da9673a5 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h @@ -262,6 +262,7 @@ extern EFI_SMM_CPU_PROTOCOL mSmmCpu; extern EFI_MM_MP_PROTOCOL mSmmMp; extern BOOLEAN m5LevelPagingNeeded; extern PAGING_MODE mPagingMode; +extern UINTN mSmmShadowStackSize; /// /// The mode of the CPU at the time an SMI occurs diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c index 0bed857cae..46d8ff5d4e 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c @@ -13,8 +13,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #define PAGE_TABLE_PAGES 8 #define ACC_MAX_BIT BIT3 -extern UINTN mSmmShadowStackSize; - LIST_ENTRY mPagePool = INITIALIZE_LIST_HEAD_VARIABLE (mPagePool); BOOLEAN m1GPageTableSupport = FALSE; BOOLEAN mCpuSmmRestrictedMemoryAccess; diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c index 00a284c369..c4f21e2155 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c @@ -1,7 +1,7 @@ /** @file SMM CPU misc functions for x64 arch specific. -Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.
+Copyright (c) 2015 - 2023, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -12,7 +12,6 @@ EFI_PHYSICAL_ADDRESS mGdtBuffer; UINTN mGdtBufferSize; extern BOOLEAN mCetSupported; -extern UINTN mSmmShadowStackSize; X86_ASSEMBLY_PATCH_LABEL mPatchCetPl0Ssp; X86_ASSEMBLY_PATCH_LABEL mPatchCetInterruptSsp; -- 2.31.1.windows.1