From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by mx.groups.io with SMTP id smtpd.web10.916.1686193607701518790 for ; Wed, 07 Jun 2023 20:06:51 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=CO7jdZba; spf=pass (domain: intel.com, ip: 192.55.52.136, mailfrom: zhiguang.liu@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1686193611; x=1717729611; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=S3mGWZJ8k853p42vuMbW4htTEKrSnt7HHtLPvy4EofA=; b=CO7jdZbacMN231KECBVnHGdumbu37SaqL5hd8Ph/5X7P4cTj+HT4bRAY /GwLrhCUtZQfVRqMC8LacsUAWXB78YJSfyKWpE+Gtg1rUUChXl4YY5n1E Ih6pgqOA672bv8WSR9qJgZvGAr3AvxnExjn4EgNaarvmMkEWbwnsrfELE L6hmxQgQAblQINh6Qs7JrKWGRQqCFtby8KK36mfZE3BkmG6rDm0JPScvV ZT6NLqwyKObRYFkKuY9BRJ/rIwuUoppIsAS0mSnDCRjyNX4sdcF4ubDcC x8kJaHanSxChLKfYlhUQadm3Pdv8Gr0pI8EGb1R0QRp/bx9vJ7uaU1/Vd w==; X-IronPort-AV: E=McAfee;i="6600,9927,10734"; a="336808897" X-IronPort-AV: E=Sophos;i="6.00,226,1681196400"; d="scan'208";a="336808897" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jun 2023 20:06:50 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10734"; a="742933590" X-IronPort-AV: E=Sophos;i="6.00,226,1681196400"; d="scan'208";a="742933590" Received: from shwdesfp01.ccr.corp.intel.com ([10.239.158.151]) by orsmga001-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jun 2023 20:06:48 -0700 From: "Zhiguang Liu" To: devel@edk2.groups.io Cc: Zhiguang Liu , Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: [PATCH 3/4] UefiCpuPkg: Clean up some Mtrr code using new API Date: Thu, 8 Jun 2023 11:06:28 +0800 Message-Id: <20230608030629.2734-3-zhiguang.liu@intel.com> X-Mailer: git-send-email 2.31.1.windows.1 In-Reply-To: <20230608030629.2734-1-zhiguang.liu@intel.com> References: <20230608030629.2734-1-zhiguang.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3394 With new API GetMaxPlatformAddressBits, the API MtrrLibInitializeMtrrMask and InitializeMtrrMask can be replaced. Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann Signed-off-by: Zhiguang Liu --- UefiCpuPkg/CpuDxe/CpuDxe.c | 49 +----------------------- UefiCpuPkg/Library/MtrrLib/MtrrLib.c | 56 ++-------------------------- 2 files changed, 4 insertions(+), 101 deletions(-) diff --git a/UefiCpuPkg/CpuDxe/CpuDxe.c b/UefiCpuPkg/CpuDxe/CpuDxe.c index 804ef5d1fe..7505801c01 100644 --- a/UefiCpuPkg/CpuDxe/CpuDxe.c +++ b/UefiCpuPkg/CpuDxe/CpuDxe.c @@ -494,52 +494,6 @@ CpuSetMemoryAttributes ( return AssignMemoryPageAttributes (NULL, BaseAddress, Length, MemoryAttributes, NULL); } -/** - Initializes the valid bits mask and valid address mask for MTRRs. - - This function initializes the valid bits mask and valid address mask for MTRRs. - -**/ -VOID -InitializeMtrrMask ( - VOID - ) -{ - UINT32 MaxExtendedFunction; - CPUID_VIR_PHY_ADDRESS_SIZE_EAX VirPhyAddressSize; - UINT32 MaxFunction; - CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX ExtendedFeatureFlagsEcx; - MSR_IA32_TME_ACTIVATE_REGISTER TmeActivate; - - AsmCpuid (CPUID_EXTENDED_FUNCTION, &MaxExtendedFunction, NULL, NULL, NULL); - - if (MaxExtendedFunction >= CPUID_VIR_PHY_ADDRESS_SIZE) { - AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, &VirPhyAddressSize.Uint32, NULL, NULL, NULL); - } else { - VirPhyAddressSize.Bits.PhysicalAddressBits = 36; - } - - // - // CPUID enumeration of MAX_PA is unaffected by TME-MK activation and will continue - // to report the maximum physical address bits available for software to use, - // irrespective of the number of KeyID bits. - // So, we need to check if TME is enabled and adjust the PA size accordingly. - // - AsmCpuid (CPUID_SIGNATURE, &MaxFunction, NULL, NULL, NULL); - if (MaxFunction >= CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS) { - AsmCpuidEx (CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, 0, NULL, NULL, &ExtendedFeatureFlagsEcx.Uint32, NULL); - if (ExtendedFeatureFlagsEcx.Bits.TME_EN == 1) { - TmeActivate.Uint64 = AsmReadMsr64 (MSR_IA32_TME_ACTIVATE); - if (TmeActivate.Bits.TmeEnable == 1) { - VirPhyAddressSize.Bits.PhysicalAddressBits -= TmeActivate.Bits.MkTmeKeyidBits; - } - } - } - - mValidMtrrBitsMask = LShiftU64 (1, VirPhyAddressSize.Bits.PhysicalAddressBits) - 1; - mValidMtrrAddressMask = mValidMtrrBitsMask & 0xfffffffffffff000ULL; -} - /** Gets GCD Mem Space type from MTRR Type. @@ -740,8 +694,7 @@ RefreshMemoryAttributesFromMtrr ( // // Initialize the valid bits mask and valid address mask for MTRRs // - InitializeMtrrMask (); - + GetMaxPlatformAddressBits (&mValidMtrrBitsMask, &mValidMtrrAddressMask); // // Get the memory attribute of variable MTRRs // diff --git a/UefiCpuPkg/Library/MtrrLib/MtrrLib.c b/UefiCpuPkg/Library/MtrrLib/MtrrLib.c index 22ec8d2a48..95bf8d771f 100644 --- a/UefiCpuPkg/Library/MtrrLib/MtrrLib.c +++ b/UefiCpuPkg/Library/MtrrLib/MtrrLib.c @@ -741,56 +741,6 @@ MtrrLibTypeLeftPrecedeRight ( return (BOOLEAN)(Left == CacheUncacheable || (Left == CacheWriteThrough && Right == CacheWriteBack)); } -/** - Initializes the valid bits mask and valid address mask for MTRRs. - - This function initializes the valid bits mask and valid address mask for MTRRs. - - @param[out] MtrrValidBitsMask The mask for the valid bit of the MTRR - @param[out] MtrrValidAddressMask The valid address mask for the MTRR - -**/ -VOID -MtrrLibInitializeMtrrMask ( - OUT UINT64 *MtrrValidBitsMask, - OUT UINT64 *MtrrValidAddressMask - ) -{ - UINT32 MaxExtendedFunction; - CPUID_VIR_PHY_ADDRESS_SIZE_EAX VirPhyAddressSize; - UINT32 MaxFunction; - CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX ExtendedFeatureFlagsEcx; - MSR_IA32_TME_ACTIVATE_REGISTER TmeActivate; - - AsmCpuid (CPUID_EXTENDED_FUNCTION, &MaxExtendedFunction, NULL, NULL, NULL); - - if (MaxExtendedFunction >= CPUID_VIR_PHY_ADDRESS_SIZE) { - AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, &VirPhyAddressSize.Uint32, NULL, NULL, NULL); - } else { - VirPhyAddressSize.Bits.PhysicalAddressBits = 36; - } - - // - // CPUID enumeration of MAX_PA is unaffected by TME-MK activation and will continue - // to report the maximum physical address bits available for software to use, - // irrespective of the number of KeyID bits. - // So, we need to check if TME is enabled and adjust the PA size accordingly. - // - AsmCpuid (CPUID_SIGNATURE, &MaxFunction, NULL, NULL, NULL); - if (MaxFunction >= CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS) { - AsmCpuidEx (CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, 0, NULL, NULL, &ExtendedFeatureFlagsEcx.Uint32, NULL); - if (ExtendedFeatureFlagsEcx.Bits.TME_EN == 1) { - TmeActivate.Uint64 = AsmReadMsr64 (MSR_IA32_TME_ACTIVATE); - if (TmeActivate.Bits.TmeEnable == 1) { - VirPhyAddressSize.Bits.PhysicalAddressBits -= TmeActivate.Bits.MkTmeKeyidBits; - } - } - } - - *MtrrValidBitsMask = LShiftU64 (1, VirPhyAddressSize.Bits.PhysicalAddressBits) - 1; - *MtrrValidAddressMask = *MtrrValidBitsMask & 0xfffffffffffff000ULL; -} - /** Determines the real attribute of a memory range. @@ -900,7 +850,7 @@ MtrrGetMemoryAttributeByAddressWorker ( ASSERT (VariableMtrrCount <= ARRAY_SIZE (MtrrSetting->Variables.Mtrr)); MtrrGetVariableMtrrWorker (MtrrSetting, VariableMtrrCount, &VariableSettings); - MtrrLibInitializeMtrrMask (&MtrrValidBitsMask, &MtrrValidAddressMask); + GetMaxPlatformAddressBits (&MtrrValidBitsMask, &MtrrValidAddressMask); MtrrLibGetRawVariableRanges ( &VariableSettings, VariableMtrrCount, @@ -2298,7 +2248,7 @@ MtrrSetMemoryAttributesInMtrrSettings ( BOOLEAN MtrrContextValid; Status = RETURN_SUCCESS; - MtrrLibInitializeMtrrMask (&MtrrValidBitsMask, &MtrrValidAddressMask); + GetMaxPlatformAddressBits (&MtrrValidBitsMask, &MtrrValidAddressMask); // // TRUE indicating the accordingly Variable setting needs modificaiton in OriginalVariableMtrr. @@ -2952,7 +2902,7 @@ MtrrDebugPrintAllMtrrsWorker ( // DEBUG ((DEBUG_CACHE, "Memory Ranges:\n")); DEBUG ((DEBUG_CACHE, "====================================\n")); - MtrrLibInitializeMtrrMask (&MtrrValidBitsMask, &MtrrValidAddressMask); + GetMaxPlatformAddressBits (&MtrrValidBitsMask, &MtrrValidAddressMask); Ranges[0].BaseAddress = 0; Ranges[0].Length = MtrrValidBitsMask + 1; Ranges[0].Type = MtrrGetDefaultMemoryTypeWorker (Mtrrs); -- 2.31.1.windows.1