From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by mx.groups.io with SMTP id smtpd.web10.12006.1686660101679430320 for ; Tue, 13 Jun 2023 05:41:41 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=Io2UIpQo; spf=pass (domain: intel.com, ip: 192.55.52.120, mailfrom: hunter.chang@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1686660101; x=1718196101; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=e5X6QanM/Ohb8y87nFaZ/DwBrMJlD6T8dQb9YXZjgXc=; b=Io2UIpQoBO7I2QkPFiDWRln+lbOpzHpQQY553nxkqiQ7dTWftnrxJkFT sVApeNnfk8v3FXvffMS7SnbLV6Z8HfqoegyFm4tmpsod6fXw+hF3Sa3Dp Ha5Miha156CvePKwgYaO51EmF+Ur3ijV4o9UAwu2cMNmqz8sOmvEMYHfH XGJ+oyD5eAiD1i16OUfrrcbVv67DApm8THGuki43eR6UxoOSpJ2EzZ0+A kALRQrwdnxkNbgt9m/snicWJ5FPg9cD86OP3LkX+8nPdg1dOSuvzVpGDK DvuE/p0sPwgWjufC7YJJPUOLmo5JzJUu7Y+nRkuf6KHU/gGOOwh5nC16J w==; X-IronPort-AV: E=McAfee;i="6600,9927,10739"; a="357196198" X-IronPort-AV: E=Sophos;i="6.00,239,1681196400"; d="scan'208";a="357196198" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Jun 2023 05:41:41 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10739"; a="856073346" X-IronPort-AV: E=Sophos;i="6.00,239,1681196400"; d="scan'208";a="856073346" Received: from changhun-desk.gar.corp.intel.com ([10.5.215.139]) by fmsmga001.fm.intel.com with ESMTP; 13 Jun 2023 05:41:39 -0700 From: "Chang, Hunter" To: devel@edk2.groups.io Cc: Hunter Chang , Ray Ni , Rangasai V Chaganty , Isaac Oram , Ashraf Ali S , Tina Chen , Arthur Chen Subject: [PATCH v1] IntelSiliconPkg: Add gEndOfSiInitPpiGuid definition in DEC file Date: Tue, 13 Jun 2023 20:40:21 +0800 Message-Id: <20230613124021.3678-1-hunter.chang@intel.com> X-Mailer: git-send-email 2.26.2.windows.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: Hunter Chang REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4371 Add gEndOfSiInitPpiGuid definition in IntelSiliconPkg.dec gEndOfSiInitPpiGuid indicates the end of all of the silicon init. Add it to IntellSiliconPkg for AFP improvement. Signed-off-by: Hunter Chang Cc: Ray Ni Cc: Rangasai V Chaganty Cc: Isaac Oram Cc: Ashraf Ali S Cc: Tina Chen Cc: Arthur Chen --- Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec | 1 + 1 file changed, 1 insertion(+) diff --git a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec b/Silicon/In= tel/IntelSiliconPkg/IntelSiliconPkg.dec index ec8690a8d6..c540ef40ad 100644 --- a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec +++ b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec @@ -113,6 +113,7 @@ gEdkiiVTdInfoPpiGuid =3D { 0x8a59fcb3, 0xf191, 0x400c, { 0x97, 0x67, 0x6= 7, 0xaf, 0x2b, 0x25, 0x68, 0x4a } }=0D gEdkiiVTdNullRootEntryTableGuid =3D { 0x3de0593f, 0x6e3e, 0x4542, { 0xa1= , 0xcb, 0xcb, 0xb2, 0xdb, 0xeb, 0xd8, 0xff } }=0D gIntelDieInfoPpiGuid =3D { 0xF9E45CBF, 0x1E21, 0x434A, { 0x90, 0x88, 0x1= D, 0x10, 0x38, 0xF3, 0x68, 0xF2 }}=0D + gEndOfSiInitPpiGuid =3D { 0xE2E3D5D1, 0x8356, 0x4F96, { 0x9C, 0x9E, 0x2= E, 0xC3, 0x48, 0x1D, 0xEA, 0x88 }}=0D =0D [Protocols]=0D ## Protocols that provide services for the Intel(R) PCH SPI Host Control= ler Compatibility Interface=0D --=20 2.26.2.windows.1