From: "Marcin Juszkiewicz" <marcin.juszkiewicz@linaro.org>
To: devel@edk2.groups.io
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>,
Leif Lindholm <quic_llindhol@quicinc.com>,
Graeme Gregory <graeme@xora.org.uk>,
Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Subject: [PATCH edk2-platforms 1/3] WIP: SbsaQemu: make PCIe variables dynamic (part 1)
Date: Tue, 13 Jun 2023 21:28:58 +0200 [thread overview]
Message-ID: <20230613192900.158022-2-marcin.juszkiewicz@linaro.org> (raw)
In-Reply-To: <20230613192900.158022-1-marcin.juszkiewicz@linaro.org>
DSDT and PciHostBridge gets hardcoded values directly instead of using
FixedPcd* functions.
---
.../SbsaQemuPciHostBridgeLib.c | 16 ++++----
Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl | 38 +++++++++----------
2 files changed, 27 insertions(+), 27 deletions(-)
diff --git a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuPciHostBridgeLib/SbsaQemuPciHostBridgeLib.c b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuPciHostBridgeLib/SbsaQemuPciHostBridgeLib.c
index 9739c7500def..08e9b23c5b33 100644
--- a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuPciHostBridgeLib/SbsaQemuPciHostBridgeLib.c
+++ b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuPciHostBridgeLib/SbsaQemuPciHostBridgeLib.c
@@ -83,31 +83,31 @@ STATIC PCI_ROOT_BRIDGE mRootBridge = {
{
/* PCI_ROOT_BRIDGE_APERTURE Bus; Bus aperture which can be used by the
* root bridge. */
- FixedPcdGet32 (PcdPciBusMin),
- FixedPcdGet32 (PcdPciBusMax)
+ 0, //PcdGet32 (PcdPciBusMin),
+ 255 //PcdGet32 (PcdPciBusMax)
},
/* PCI_ROOT_BRIDGE_APERTURE Io; IO aperture which can be used by the root
bridge */
{
- FixedPcdGet64 (PcdPciIoBase),
- FixedPcdGet64 (PcdPciIoBase) + FixedPcdGet64 (PcdPciIoSize) - 1
+ 0, //PcdGet64 (PcdPciIoBase),
+ 0XFFFF //PcdGet64 (PcdPciIoBase) + PcdGet64 (PcdPciIoSize) - 1
},
/* PCI_ROOT_BRIDGE_APERTURE Mem; MMIO aperture below 4GB which can be used by
the root bridge
(gEfiMdePkgTokenSpaceGuid.PcdPciMmio32Translation as 0x0) */
{
- FixedPcdGet32 (PcdPciMmio32Base),
- FixedPcdGet32 (PcdPciMmio32Base) + FixedPcdGet32 (PcdPciMmio32Size) - 1,
+ 0x80000000, //PcdGet32 (PcdPciMmio32Base),
+ 0xEFFFFFFF //PcdGet32 (PcdPciMmio32Base) + PcdGet32 (PcdPciMmio32Size) - 1,
},
/* PCI_ROOT_BRIDGE_APERTURE MemAbove4G; MMIO aperture above 4GB which can be
used by the root bridge.
(gEfiMdePkgTokenSpaceGuid.PcdPciMmio64Translation as 0x0) */
{
- FixedPcdGet64 (PcdPciMmio64Base),
- FixedPcdGet64 (PcdPciMmio64Base) + FixedPcdGet64 (PcdPciMmio64Size) - 1
+ 0x0100000000, //PcdGet64 (PcdPciMmio64Base),
+ 0xFFFFFFFFFF //PcdGet64 (PcdPciMmio64Base) + PcdGet64 (PcdPciMmio64Size) - 1
},
/* PCI_ROOT_BRIDGE_APERTURE PMem; Prefetchable MMIO aperture below 4GB which
diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl b/Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl
index e50772fcf76d..7193c87cdcf2 100644
--- a/Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl
+++ b/Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl
@@ -198,7 +198,7 @@ DefinitionBlock ("DsdtTable.aml", "DSDT",
}
Method (_CBA, 0, NotSerialized) {
- return (FixedPcdGet32 (PcdPciExpressBaseAddress))
+ return (0xF0000000) // return (PcdGet32 (PcdPciExpressBaseAddress))
}
LINK_DEVICE(0, GSI0, 0x23)
@@ -376,8 +376,8 @@ DefinitionBlock ("DsdtTable.aml", "DSDT",
ResourceProducer,
MinFixed, MaxFixed, PosDecode,
0, // AddressGranularity
- FixedPcdGet32 (PcdPciBusMin), // AddressMinimum - Minimum Bus Number
- FixedPcdGet32 (PcdPciBusMax), // AddressMaximum - Maximum Bus Number
+ 0, // PcdGet32 (PcdPciBusMin), // AddressMinimum - Minimum Bus Number
+ 255, // PcdGet32 (PcdPciBusMax), // AddressMaximum - Maximum Bus Number
0, // AddressTranslation - Set to 0
256 // RangeLength - Number of Busses
)
@@ -387,10 +387,10 @@ DefinitionBlock ("DsdtTable.aml", "DSDT",
MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, // Granularity
- FixedPcdGet32 (PcdPciMmio32Base), // Min Base Address
- FixedPcdGet32 (PcdPciMmio32Limit), // Max Base Address
- FixedPcdGet32 (PcdPciMmio32Translation), // Translate
- FixedPcdGet32 (PcdPciMmio32Size) // Length
+ 0x80000000, // PcdGet32 (PcdPciMmio32Base), // Min Base Address
+ 0xEFFFFFFF, // PcdGet32 (PcdPciMmio32Limit), // Max Base Address
+ 0, // PcdGet32 (PcdPciMmio32Translation), // Translate
+ 0x70000000, // PcdGet32 (PcdPciMmio32Size) // Length
)
QWordMemory ( // 64-bit BAR Windows
@@ -398,10 +398,10 @@ DefinitionBlock ("DsdtTable.aml", "DSDT",
MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, // Granularity
- FixedPcdGet64 (PcdPciMmio64Base), // Min Base Address
- FixedPcdGet64 (PcdPciMmio64Limit), // Max Base Address
- FixedPcdGet64 (PcdPciMmio64Translation), // Translate
- FixedPcdGet64 (PcdPciMmio64Size) // Length
+ 0x100000000, // PcdGet64 (PcdPciMmio64Base), // Min Base Address
+ 0xFFFFFFFFFF, // PcdGet64 (PcdPciMmio64Limit), // Max Base Address
+ 0, // PcdGet64 (PcdPciMmio64Translation), // Translate
+ 0xFF00000000, // PcdGet64 (PcdPciMmio64Size) // Length
)
DWordIo ( // IO window
@@ -411,10 +411,10 @@ DefinitionBlock ("DsdtTable.aml", "DSDT",
PosDecode,
EntireRange,
0x00000000, // Granularity
- FixedPcdGet32 (PcdPciIoBase), // Min Base Address
- FixedPcdGet32 (PcdPciIoLimit), // Max Base Address
- FixedPcdGet32 (PcdPciIoTranslation), // Translate
- FixedPcdGet32 (PcdPciIoSize), // Length
+ 0, // PcdGet32 (PcdPciIoBase), // Min Base Address
+ 0x0000ffff, // PcdGet32 (PcdPciIoLimit), // Max Base Address
+ 0x7fff0000, // PcdGet32 (PcdPciIoTranslation), // Translate
+ 0x00010000, // PcdGet32 (PcdPciIoSize), // Length
,,,TypeTranslation
)
}) // Name(RBUF)
@@ -429,10 +429,10 @@ DefinitionBlock ("DsdtTable.aml", "DSDT",
{
QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
0x0000000000000000, // Granularity
- FixedPcdGet64 (PcdPciExpressBaseAddress), // Range Minimum
- FixedPcdGet64 (PcdPciExpressBarLimit), // Range Maximum
- 0x0000000000000000, // Translation Offset
- FixedPcdGet64 (PcdPciExpressBarSize), // Length
+ 0xf0000000, // PcdGet64 (PcdPciExpressBaseAddress), // Range Minimum
+ 0xFFFFFFFF, // PcdGet64 (PcdPciExpressBarLimit), // Range Maximum
+ 0x0000000000000000, // Translation Offset
+ 0x10000000, // PcdGet64 (PcdPciExpressBarSize), // Length
,, , AddressRangeMemory, TypeStatic)
})
Method (_STA) {
--
2.40.1
next prev parent reply other threads:[~2023-06-13 19:29 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-13 19:28 [PATCH edk2-platforms 0/3] WIP: SbsaQemu: make PCIe dynamic Marcin Juszkiewicz
2023-06-13 19:28 ` Marcin Juszkiewicz [this message]
2023-06-13 19:28 ` [PATCH edk2-platforms 2/3] WIP: SbsaQemu: make PCIe variables dynamic (part 2) Marcin Juszkiewicz
2023-06-13 19:29 ` [PATCH edk2-platforms 3/3] WIP: SbsaQemu: make PCIe variables dynamic (part 3) Marcin Juszkiewicz
2023-06-21 12:15 ` [PATCH edk2-platforms 0/3] WIP: SbsaQemu: make PCIe dynamic Marcin Juszkiewicz
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