From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pf1-f182.google.com (mail-pf1-f182.google.com [209.85.210.182]) by mx.groups.io with SMTP id smtpd.web10.18169.1686762124978230603 for ; Wed, 14 Jun 2023 10:02:05 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="signature has expired" header.i=@ventanamicro.com header.s=google header.b=gx2HXJkH; spf=pass (domain: ventanamicro.com, ip: 209.85.210.182, mailfrom: sunilvl@ventanamicro.com) Received: by mail-pf1-f182.google.com with SMTP id d2e1a72fcca58-66577752f05so2893200b3a.0 for ; Wed, 14 Jun 2023 10:02:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1686762124; x=1689354124; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=mNOZsuroQoDWpzqbrzSnVz3NEh4LGNW93Ho7PYHHhLk=; b=gx2HXJkH3grb/mcqili74mDbQ+LtGkhSgKS2rIEb0k5GOG90Z6k7MEJkm/hfAdXQFG 45z6BxtW9aE3CADg14MQFpbVsocX2c9DTgp/ADtF8mwjb4wX+JIPfWVZgtnzUHZSC8r/ xrd1S2lDCJ4zIWSZavPIdfwl1O9BhtBXfFsE/pvq0i7Sr/kriRTPholVkfs5upUCtjOn XxehrGTj7maeeud3KgV34daNejfVcxlIQO9E8JFAu/gqrI3ab1YOz02QpIpc5p9hf3ia 89ZkMDc6s/b1ydW0u6is67nrJ5y1KXDlLymHJWOOU45hJBny7S9qxTySXOuZhvzYRcup TZuA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686762124; x=1689354124; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mNOZsuroQoDWpzqbrzSnVz3NEh4LGNW93Ho7PYHHhLk=; b=MSytca2cjeo6KXJ/CFPh8Ejy9Hcs1bHBwsYNLaT31DRd5saTbTp/RucooV3d6xfIPh MAqVSg0sJ11yjcRP8X17ncohMazNtz6RLc5SOuJLAmCfzU8IwR2im2PLMLZY9ul8zYdD DkswkTqj+OanN7yceI92Jyr6gJekYq58Y25rCs/UR8fN1mgQJSHwbs/6n5fDZat6GUsW J0VBQ/IomIK2dlnj84MvtKR1DhyXnn1NRBgVHteQmdeP8w3xYCYgti2t7VYnf6OkXyWW FNWWBJtUBvTzEPknZjehLMs5AWI2wCWlq3hh14NSPpn5eNc4Qp+7r6O08iuTVJ+WYUCA O74g== X-Gm-Message-State: AC+VfDybpMPi5wdNlnnW6BQGwkRMnqN07oQ1dmJLkAsiRaUgwoWs0a1t wyBPlCDGClp4Zj7g0HpYaMG5CJG2JQHLE98g6A4= X-Google-Smtp-Source: ACHHUZ7MfX4gJs0nq0XXhl5fSrFGOLb13MEUiw7+MyDgh+geNDr62ehnqMhkF+l1m+83J9s3FjoZhA== X-Received: by 2002:a17:902:d4cf:b0:1af:d213:668c with SMTP id o15-20020a170902d4cf00b001afd213668cmr14562316plg.12.1686762124252; Wed, 14 Jun 2023 10:02:04 -0700 (PDT) Return-Path: Received: from kerodi.Dlink ([106.51.184.72]) by smtp.gmail.com with ESMTPSA id s7-20020a170902988700b001b3ef11d8fdsm1850424plp.201.2023.06.14.10.02.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Jun 2023 10:02:03 -0700 (PDT) From: "Sunil V L" To: devel@edk2.groups.io Cc: Sunil V L , Ard Biesheuvel , Jiewen Yao , Jordan Justen , Gerd Hoffmann , Andrei Warkentin Subject: [PATCH 3/4] OvmfPkg/RiscVVirt: Add support for separate code and variable store Date: Wed, 14 Jun 2023 22:31:50 +0530 Message-Id: <20230614170151.1204982-4-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230614170151.1204982-1-sunilvl@ventanamicro.com> References: <20230614170151.1204982-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Currently, RiscVVirtQemu supports unified code and variable store mainly because only one pflash devices was available in qemu for EDK2. However, this doesn't allow to map the code part as read-only. With recent qemu enhancements, it is now possible for EDK2 to make use of both pflash devices in RISC-V virt machine. So, add support to create code and vars images separately. This also allows easy firmware code updates without losing the variable store. Signed-off-by: Sunil V L Cc: Ard Biesheuvel Cc: Jiewen Yao Cc: Jordan Justen Cc: Gerd Hoffmann Cc: Andrei Warkentin --- OvmfPkg/RiscVVirt/RiscVVirtQemu.dsc | 2 +- OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf | 9 +++++---- OvmfPkg/RiscVVirt/RiscVVirt.fdf.inc | 12 +++++------- OvmfPkg/RiscVVirt/VarStore.fdf.inc | 13 ++++++++++--- 4 files changed, 21 insertions(+), 15 deletions(-) diff --git a/OvmfPkg/RiscVVirt/RiscVVirtQemu.dsc b/OvmfPkg/RiscVVirt/RiscVVirtQemu.dsc index 414d186179fb..04573bc0f32e 100644 --- a/OvmfPkg/RiscVVirt/RiscVVirtQemu.dsc +++ b/OvmfPkg/RiscVVirt/RiscVVirtQemu.dsc @@ -85,7 +85,7 @@ [LibraryClasses.common] QemuLoadImageLib|OvmfPkg/Library/GenericQemuLoadImageLib/GenericQemuLoadImageLib.inf TimerLib|UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/BaseRiscV64CpuTimerLib.inf - VirtNorFlashPlatformLib|OvmfPkg/RiscVVirt/Library/VirtNorFlashPlatformLib/VirtNorFlashStaticLib.inf + VirtNorFlashPlatformLib|OvmfPkg/RiscVVirt/Library/VirtNorFlashPlatformLib/VirtNorFlashDeviceTreeLib.inf CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf diff --git a/OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf b/OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf index 354c9271d10c..dbe38a135395 100644 --- a/OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf +++ b/OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf @@ -12,17 +12,18 @@ !include RiscVVirt.fdf.inc ################################################################################ -[FD.RISCV_VIRT] -BaseAddress = $(FW_BASE_ADDRESS)|gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFdBaseAddress -Size = $(FW_SIZE)|gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFirmwareFdSize +[FD.RISCV_VIRT_CODE] +BaseAddress = $(CODE_BASE_ADDRESS)|gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFdBaseAddress +Size = $(CODE_SIZE)|gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFirmwareFdSize ErasePolarity = 1 BlockSize = $(BLOCK_SIZE) -NumBlocks = $(FW_BLOCKS) +NumBlocks = $(CODE_BLOCKS) 0x00000000|$(CODE_SIZE) gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDxeMemFvBase|gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDxeMemFvSize FV = FVMAIN_COMPACT +################################################################################ !include VarStore.fdf.inc ################################################################################ diff --git a/OvmfPkg/RiscVVirt/RiscVVirt.fdf.inc b/OvmfPkg/RiscVVirt/RiscVVirt.fdf.inc index b0a1c3293f33..7e8165d85778 100644 --- a/OvmfPkg/RiscVVirt/RiscVVirt.fdf.inc +++ b/OvmfPkg/RiscVVirt/RiscVVirt.fdf.inc @@ -10,16 +10,14 @@ [Defines] DEFINE BLOCK_SIZE = 0x1000 +DEFINE PFLASH0_BASE = 0x20000000 DEFINE PFLASH1_BASE = 0x22000000 -DEFINE FW_BASE_ADDRESS = $(PFLASH1_BASE) -DEFINE FW_SIZE = 0x00800000 -DEFINE FW_BLOCKS = 0x800 - -DEFINE CODE_BASE_ADDRESS = $(FW_BASE_ADDRESS) -DEFINE CODE_SIZE = 0x00740000 -DEFINE CODE_BLOCKS = 0x740 +DEFINE CODE_BASE_ADDRESS = $(PFLASH0_BASE) +DEFINE CODE_SIZE = 0x00800000 +DEFINE CODE_BLOCKS = 0x800 +DEFINE VARS_BASE_ADDRESS = $(PFLASH1_BASE) DEFINE VARS_SIZE = 0x000C0000 DEFINE VARS_BLOCK_SIZE = 0x40000 DEFINE VARS_BLOCKS = 0x3 diff --git a/OvmfPkg/RiscVVirt/VarStore.fdf.inc b/OvmfPkg/RiscVVirt/VarStore.fdf.inc index 6bc619e50c1a..49293c742b56 100644 --- a/OvmfPkg/RiscVVirt/VarStore.fdf.inc +++ b/OvmfPkg/RiscVVirt/VarStore.fdf.inc @@ -10,7 +10,14 @@ # ## -$(VARS_OFFSET)|$(VARS_LIVE_SIZE) +[FD.RISCV_VIRT_VARS] +BaseAddress = $(VARS_BASE_ADDRESS) +Size = $(VARS_SIZE) +ErasePolarity = 1 +BlockSize = $(VARS_BLOCK_SIZE) +NumBlocks = $(VARS_BLOCKS) + +0x00000000|$(VARS_LIVE_SIZE) gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize # # NV_VARIABLE_STORE @@ -57,7 +64,7 @@ 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } -$(VARS_FTW_WORKING_OFFSET)|$(VARS_FTW_WORKING_SIZE) +0x00040000|$(VARS_FTW_WORKING_SIZE) gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize # #NV_FTW_WORK @@ -73,7 +80,7 @@ 0xE0, 0xFF, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00 } -$(VARS_FTW_SPARE_OFFSET)|$(VARS_FTW_SPARE_SIZE) +0x00080000|$(VARS_FTW_SPARE_SIZE) gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize # #NV_FTW_SPARE -- 2.34.1