From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by mx.groups.io with SMTP id smtpd.web10.15125.1686826271830570395 for ; Thu, 15 Jun 2023 03:51:12 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=TY9I1PPH; spf=pass (domain: intel.com, ip: 192.55.52.88, mailfrom: ray.ni@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1686826271; x=1718362271; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=l0VjxjsqRyEowG8EeepBsY6rpVYC57EkTsJFRB2g7n4=; b=TY9I1PPHDJaJ/hvSVUW+XTWCzCf8QNXAZOBVQLxrY9VHNRP8Emr94qLs VoLMGyb+OTxCgwZjh8ct7FsY4fq9k0O6tm4NzGWqj3aNUzEngKNQfkl/j bBH2rN22tCHr+ZC5ovM/YDEuHp8e5LD7mVm5n9uft662WMiS2YCvw8asI +7vGsIuRF6Y/HHWljfHkic1pBk5E68S9+GDgM+6KwWcszp3XP7S/vaQJK h1XMOAEzBFlwJw8YsVjaEoDqpTgfmZTN7PQoezmIHCpDzk4TS1O36mfce +58ajB02HDkqJU9pFK7rXd/99ryuDot+QIIKT6ED5YjkdDktjMKP/erE9 Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10741"; a="387323154" X-IronPort-AV: E=Sophos;i="6.00,244,1681196400"; d="scan'208";a="387323154" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Jun 2023 03:51:11 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10741"; a="959156162" X-IronPort-AV: E=Sophos;i="6.00,244,1681196400"; d="scan'208";a="959156162" Received: from shwdeopenlab706.ccr.corp.intel.com ([10.239.55.95]) by fmsmga006.fm.intel.com with ESMTP; 15 Jun 2023 03:51:01 -0700 From: "Ni, Ray" To: devel@edk2.groups.io Cc: Eric Dong , Rahul Kumar , Gerd Hoffmann Subject: [PATCH 2/3] UefiCpuPkg/ResetVector: Add guidance of how to guarantee 16B align Date: Thu, 15 Jun 2023 18:50:56 +0800 Message-Id: <20230615105057.297-3-ray.ni@intel.com> X-Mailer: git-send-email 2.39.1.windows.1 In-Reply-To: <20230615105057.297-1-ray.ni@intel.com> References: <20230615105057.297-1-ray.ni@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable ResetVector assembly implementation puts "ALIGN 16" in the end to guarantee the final executable file size is multiple of 16 bytes. Because the module uses a special GUID which guarantees it's put in the very end of a FV, which should be also the end of the FD. Then to make sure the reset vector "JMP" code is at FFFF_FFF0h, the ResetVector has to be aligned at 16-byte boundary. The patch updates INF file and ReadMe.txt to add guidance how to make sure the module is aligned on 16-byte boundary. Signed-off-by: Ray Ni Cc: Eric Dong Cc: Rahul Kumar Cc: Gerd Hoffmann --- UefiCpuPkg/ResetVector/Vtf0/ReadMe.txt | 27 +++++++------------------- UefiCpuPkg/ResetVector/Vtf0/Vtf0.inf | 19 +++++++++++++++++- 2 files changed, 25 insertions(+), 21 deletions(-) diff --git a/UefiCpuPkg/ResetVector/Vtf0/ReadMe.txt b/UefiCpuPkg/ResetVecto= r/Vtf0/ReadMe.txt index 97f4600968..edeb2d6d3e 100644 --- a/UefiCpuPkg/ResetVector/Vtf0/ReadMe.txt +++ b/UefiCpuPkg/ResetVector/Vtf0/ReadMe.txt @@ -1,15 +1,16 @@ =0D =3D=3D=3D HOW TO USE VTF0 =3D=3D=3D=0D +Add this line to your DSC [Components.IA32] or [Components.X64] section:=0D + UefiCpuPkg/ResetVector/Vtf0/ResetVector.inf=0D =0D Add this line to your FDF FV section:=0D -INF RuleOverride=3DRESET_VECTOR USE =3D IA32 UefiCpuPkg/ResetVector/Vtf0/= Bin/ResetVector.inf=0D -(For X64 SEC/PEI change IA32 to X64 =3D> 'USE =3D X64')=0D + INF RuleOverride=3DRESET_VECTOR UefiCpuPkg/ResetVector/Vtf0/ResetVector= .inf=0D =0D In your FDF FFS file rules sections add:=0D -[Rule.Common.SEC.RESET_VECTOR]=0D - FILE RAW =3D $(NAMED_GUID) {=0D - RAW RAW |.raw=0D - }=0D + [Rule.Common.SEC.RESET_VECTOR]=0D + FILE RAW =3D $(NAMED_GUID) {=0D + RAW BIN Align =3D 16 |.bin=0D + }=0D =0D =3D=3D=3D VTF0 Boot Flow =3D=3D=3D=0D =0D @@ -25,17 +26,3 @@ All inputs to SEC image are register based: EAX/RAX - Initial value of the EAX register (BIST: Built-in Self Test)=0D DI - 'BP': boot-strap processor, or 'AP': application processor=0D EBP/RBP - Pointer to the start of the Boot Firmware Volume=0D -=0D -=3D=3D=3D HOW TO BUILD VTF0 =3D=3D=3D=0D -=0D -Dependencies:=0D -* Python 3 or newer=0D -* Nasm 2.03 or newer=0D -=0D -To rebuild the VTF0 binaries:=0D -1. Change to VTF0 source dir: UefiCpuPkg/ResetVector/Vtf0=0D -2. nasm and python should be in executable path=0D -3. Run this command:=0D - python Build.py=0D -4. Binaries output will be in UefiCpuPkg/ResetVector/Vtf0/Bin=0D -=0D diff --git a/UefiCpuPkg/ResetVector/Vtf0/Vtf0.inf b/UefiCpuPkg/ResetVector/= Vtf0/Vtf0.inf index 9922cb2755..28185a6e60 100644 --- a/UefiCpuPkg/ResetVector/Vtf0/Vtf0.inf +++ b/UefiCpuPkg/ResetVector/Vtf0/Vtf0.inf @@ -1,7 +1,24 @@ ## @file=0D # Reset Vector=0D #=0D -# Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.
= =0D +# Note:=0D +# The platform FDF file MUST guarantee the ResetVector is aligned=0D +# on 16-byte boundary. Otherwise, the CPU reset vector will NOT be=0D +# at FFFF_FFF0h.=0D +#=0D +# A sample FDF build rule could be as follows:=0D +#=0D +# [Rule.Common.SEC.RESET_VECTOR]=0D +# FILE RAW =3D $(NAMED_GUID) {=0D +# RAW BIN Align =3D 16 |.bin=0D +# }=0D +#=0D +# Following line in FDF forces to use the above build rule for the Rese= tVector:=0D +#=0D +# INF RuleOverride=3DRESET_VECTOR UefiCpuPkg/ResetVector/Vtf0/Vtf0.i= nf=0D +#=0D +#=0D +# Copyright (c) 2006 - 2023, Intel Corporation. All rights reserved.
= =0D #=0D # SPDX-License-Identifier: BSD-2-Clause-Patent=0D #=0D --=20 2.39.1.windows.1