From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pf1-f175.google.com (mail-pf1-f175.google.com [209.85.210.175]) by mx.groups.io with SMTP id smtpd.web10.5097.1686910625304848699 for ; Fri, 16 Jun 2023 03:17:05 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="signature has expired" header.i=@ventanamicro.com header.s=google header.b=j4NuNh4Q; spf=pass (domain: ventanamicro.com, ip: 209.85.210.175, mailfrom: sunilvl@ventanamicro.com) Received: by mail-pf1-f175.google.com with SMTP id d2e1a72fcca58-666748c1edfso521383b3a.2 for ; Fri, 16 Jun 2023 03:17:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1686910624; x=1689502624; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=IJG1lvbFHKl8rCtDrT/3IG56zJHYxIzPOTC9CrTuOUU=; b=j4NuNh4QjTu1DowWI16OYxN0ziKgb1EGDQApI3hckpsVRM1Ap3MPSWKPhlV8HtifOg gMk+hUNYuQPw7SLoizKejON9Oi7xPZEJqJqviwfDeldOuNdNp2tNrQ8Uv38I3a2tnQHm 3uXvbwf8iCNnBvKHWObQioCWYC237/mtPWfOjMH79eKcBXx1t6oA6fqgmrgAYjBo3E47 tlI0Vc8zx4p8z9m3yh1QD95YQGct13M3KOoo5jGCTxkxmp4i5Fx2OXxSiuNMA8qDg+eP fDbiXnufFP3s1PvcKhoS8SGVZo1FVkWXGchkW485wAPeE/3XFwfbUBDqon6CTr3E7gj2 ptwQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686910624; x=1689502624; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IJG1lvbFHKl8rCtDrT/3IG56zJHYxIzPOTC9CrTuOUU=; b=K6knxOZHoMwgmaEE1aeEWbDTN+QBPT3xK/kkA/AOLpYgxAB29r52BU3IhBP19oOuK4 5GcDfjQiYwUcQJrdVDE10GIDk2KDJmymolIBLdnCzzW/moTsQJqM/BPyyJcWiYekx5MR INkB0FYIEGXuIRkPEJ1CDK3H2BM66q/pFoFj0QAvEVDbpEE5zUxpdC45FzhoHscGx0DP MPeBXEdyCaN8UBVMEYqpwFvkfKlfm4hj8THOhmAMa6dp21V2SMKKqtRiVXwEnnZAT0tO JLYqpAjeXvrNOfgVq2CBR5Vb7eRxAiYufswrlk1U141ESq7typfbJ5C57SA/AAgXR3dW 8tAQ== X-Gm-Message-State: AC+VfDxK9SDo/1E3BGpiP3jH7GK3yq2FCYQrLy+5rcatpxGrGWLItW4l w/TNHC4ays6pNAaUUOAaxELToDUxSxDL99ZZRIU= X-Google-Smtp-Source: ACHHUZ7xKVslcSrK+kc6VL92QcjRjBPIqcQKjim6p/eb+Ac9EQMOGk5baZFnfUfszZNAVk3JC9detw== X-Received: by 2002:a05:6a20:7d87:b0:110:f65a:13fb with SMTP id v7-20020a056a207d8700b00110f65a13fbmr2104842pzj.15.1686910624605; Fri, 16 Jun 2023 03:17:04 -0700 (PDT) Return-Path: Received: from kerodi.Dlink ([106.51.184.72]) by smtp.gmail.com with ESMTPSA id h12-20020a170902f54c00b001a1a82fc6d3sm15435565plf.268.2023.06.16.03.17.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Jun 2023 03:17:04 -0700 (PDT) From: "Sunil V L" To: devel@edk2.groups.io Cc: Sunil V L , Ard Biesheuvel , Jiewen Yao , Jordan Justen , Gerd Hoffmann , Andrei Warkentin Subject: [PATCH v2 3/4] OvmfPkg/RiscVVirt: Add support for separate code and variable store Date: Fri, 16 Jun 2023 15:46:50 +0530 Message-Id: <20230616101651.1319722-4-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230616101651.1319722-1-sunilvl@ventanamicro.com> References: <20230616101651.1319722-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Currently, RiscVVirtQemu supports unified code and variable store mainly because only one pflash devices was available in qemu for EDK2. However, this doesn't allow to map the code part as read-only. With recent qemu enhancements, it is now possible for EDK2 to make use of both pflash devices in RISC-V virt machine. So, add support to create code and vars images separately. This also allows easy firmware code updates without losing the variable store. Signed-off-by: Sunil V L Cc: Ard Biesheuvel Cc: Jiewen Yao Cc: Jordan Justen Cc: Gerd Hoffmann Cc: Andrei Warkentin --- OvmfPkg/RiscVVirt/RiscVVirtQemu.dsc | 2 +- OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf | 16 ++++++++++++---- OvmfPkg/RiscVVirt/RiscVVirt.fdf.inc | 14 ++++++-------- 3 files changed, 19 insertions(+), 13 deletions(-) diff --git a/OvmfPkg/RiscVVirt/RiscVVirtQemu.dsc b/OvmfPkg/RiscVVirt/RiscVVirtQemu.dsc index 414d186179fb..04573bc0f32e 100644 --- a/OvmfPkg/RiscVVirt/RiscVVirtQemu.dsc +++ b/OvmfPkg/RiscVVirt/RiscVVirtQemu.dsc @@ -85,7 +85,7 @@ [LibraryClasses.common] QemuLoadImageLib|OvmfPkg/Library/GenericQemuLoadImageLib/GenericQemuLoadImageLib.inf TimerLib|UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/BaseRiscV64CpuTimerLib.inf - VirtNorFlashPlatformLib|OvmfPkg/RiscVVirt/Library/VirtNorFlashPlatformLib/VirtNorFlashStaticLib.inf + VirtNorFlashPlatformLib|OvmfPkg/RiscVVirt/Library/VirtNorFlashPlatformLib/VirtNorFlashDeviceTreeLib.inf CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf diff --git a/OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf b/OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf index 354c9271d10c..21e4ba67379f 100644 --- a/OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf +++ b/OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf @@ -12,17 +12,25 @@ !include RiscVVirt.fdf.inc ################################################################################ -[FD.RISCV_VIRT] -BaseAddress = $(FW_BASE_ADDRESS)|gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFdBaseAddress -Size = $(FW_SIZE)|gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFirmwareFdSize +[FD.RISCV_VIRT_CODE] +BaseAddress = $(CODE_BASE_ADDRESS)|gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFdBaseAddress +Size = $(CODE_SIZE)|gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFirmwareFdSize ErasePolarity = 1 BlockSize = $(BLOCK_SIZE) -NumBlocks = $(FW_BLOCKS) +NumBlocks = $(CODE_BLOCKS) 0x00000000|$(CODE_SIZE) gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDxeMemFvBase|gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDxeMemFvSize FV = FVMAIN_COMPACT +################################################################################ +[FD.RISCV_VIRT_VARS] +BaseAddress = $(VARS_BASE_ADDRESS) +Size = $(VARS_SIZE) +ErasePolarity = 1 +BlockSize = $(VARS_BLOCK_SIZE) +NumBlocks = $(VARS_BLOCKS) + !include VarStore.fdf.inc ################################################################################ diff --git a/OvmfPkg/RiscVVirt/RiscVVirt.fdf.inc b/OvmfPkg/RiscVVirt/RiscVVirt.fdf.inc index b0a1c3293f33..eba612372fee 100644 --- a/OvmfPkg/RiscVVirt/RiscVVirt.fdf.inc +++ b/OvmfPkg/RiscVVirt/RiscVVirt.fdf.inc @@ -10,16 +10,14 @@ [Defines] DEFINE BLOCK_SIZE = 0x1000 +DEFINE PFLASH0_BASE = 0x20000000 DEFINE PFLASH1_BASE = 0x22000000 -DEFINE FW_BASE_ADDRESS = $(PFLASH1_BASE) -DEFINE FW_SIZE = 0x00800000 -DEFINE FW_BLOCKS = 0x800 - -DEFINE CODE_BASE_ADDRESS = $(FW_BASE_ADDRESS) -DEFINE CODE_SIZE = 0x00740000 -DEFINE CODE_BLOCKS = 0x740 +DEFINE CODE_BASE_ADDRESS = $(PFLASH0_BASE) +DEFINE CODE_SIZE = 0x00800000 +DEFINE CODE_BLOCKS = 0x800 +DEFINE VARS_BASE_ADDRESS = $(PFLASH1_BASE) DEFINE VARS_SIZE = 0x000C0000 DEFINE VARS_BLOCK_SIZE = 0x40000 DEFINE VARS_BLOCKS = 0x3 @@ -29,7 +27,7 @@ [Defines] # The total size of EFI Variable FD must include # all of sub regions of EFI Variable # -DEFINE VARS_OFFSET = $(CODE_SIZE) +DEFINE VARS_OFFSET = 0x00000000 DEFINE VARS_LIVE_SIZE = 0x00040000 DEFINE VARS_FTW_WORKING_OFFSET = $(VARS_OFFSET) + $(VARS_LIVE_SIZE) DEFINE VARS_FTW_WORKING_SIZE = 0x00040000 -- 2.34.1