From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pf1-f181.google.com (mail-pf1-f181.google.com [209.85.210.181]) by mx.groups.io with SMTP id smtpd.web10.5098.1686910627743188291 for ; Fri, 16 Jun 2023 03:17:07 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@ventanamicro.com header.s=google header.b=i9OVVq1s; spf=pass (domain: ventanamicro.com, ip: 209.85.210.181, mailfrom: sunilvl@ventanamicro.com) Received: by mail-pf1-f181.google.com with SMTP id d2e1a72fcca58-6664a9f0b10so521635b3a.0 for ; Fri, 16 Jun 2023 03:17:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1686910627; x=1689502627; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=jl5xiH9nvSEV3Ycb1oBJSw/56CqRn6Nm1Vt3NuLlliM=; b=i9OVVq1sUZcjeB2Pi4r73a5GIZW1ZDZmnW4YuT6KYEtV/ynuHIWsiaBkShN9RXPshk ssRatNHNhKDiNjHAnt9r3uinA4xfnUdPeJAt+S258/L9q3Y5bvq8pQFr5aCsB52VAPl1 r4utPGv9qnuVXHmbrj5SdciRXZZhmkOSAvVcBc4OgX64jsDtkTdybgJb/ZHq7NAuGvg0 EveSwAt12mE0A1kjIbhBiiyR4ChEHLFjBLftrXSJPlqen80yIkpAHqzspb6RsrWaq9xu 9ZtahpsbZi4ZdhyKCVt5RBKVJ6mrl4R2v5oeDMH7bQQkJVndKl6qeE9qvH5o1cLCjMwg UiFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686910627; x=1689502627; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jl5xiH9nvSEV3Ycb1oBJSw/56CqRn6Nm1Vt3NuLlliM=; b=KBMw5i8rK5RQO++HNfZ5jSDefa/c7RiBPhvsOxBqkc2rQt8pRleQfO1UXcrowBKDTI upwjUINJqDM+HA1mHgU90E2r7qAE1r9u2dshywBrpw0VhVL0Hij1hJRrBIOXea0BzReJ odkIr65hkOPn5hbjHNyhzqE1dzfGzAyMVg971mXJ9XkPHoYyMPDOM48MnJWjs+8l14Qm sfuZHYkh6icyx6qVExSzgNi5pvjkLuhlFMmC78yKIiLHQ8/boPVHTODZsNes/J5AZa5D 60ElRq6PUDVU5DOEbn9eSZ/1NsIS+HYaxPEZkbMUB6eLutkGU6WOK5dkIds2KBHNKjgh VjQQ== X-Gm-Message-State: AC+VfDwtuHnysnGqdYbxmXv7/Sri1kGzFoeftJI1syZROmpNlzOTq5/z Fw6Pfguavji+z9QlH2QSLwQE9SWpLHTKMpcfA8w= X-Google-Smtp-Source: ACHHUZ7eGgrk+yZ5p0X/ItAoHGStwKySK3Av9+LkrK27KspMPY3gzux6zFUZgdQsLlukZGKGm/sUMA== X-Received: by 2002:a05:6a20:7295:b0:11e:7ced:3391 with SMTP id o21-20020a056a20729500b0011e7ced3391mr1864787pzk.43.1686910627064; Fri, 16 Jun 2023 03:17:07 -0700 (PDT) Return-Path: Received: from kerodi.Dlink ([106.51.184.72]) by smtp.gmail.com with ESMTPSA id h12-20020a170902f54c00b001a1a82fc6d3sm15435565plf.268.2023.06.16.03.17.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Jun 2023 03:17:06 -0700 (PDT) From: "Sunil V L" To: devel@edk2.groups.io Cc: Sunil V L , Ard Biesheuvel , Jiewen Yao , Jordan Justen , Gerd Hoffmann , Andrei Warkentin Subject: [PATCH v2 4/4] OvmfPkg/RiscVVirt: Add a readme for build and test Date: Fri, 16 Jun 2023 15:46:51 +0530 Message-Id: <20230616101651.1319722-5-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230616101651.1319722-1-sunilvl@ventanamicro.com> References: <20230616101651.1319722-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add a readme file which provides information regarding how to build and test EDK2 on RISC-V qemu virt platform. Signed-off-by: Sunil V L Cc: Ard Biesheuvel Cc: Jiewen Yao Cc: Jordan Justen Cc: Gerd Hoffmann Cc: Andrei Warkentin --- OvmfPkg/RiscVVirt/README.md | 46 +++++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) create mode 100644 OvmfPkg/RiscVVirt/README.md diff --git a/OvmfPkg/RiscVVirt/README.md b/OvmfPkg/RiscVVirt/README.md new file mode 100644 index 000000000000..b07d5b6d3bf9 --- /dev/null +++ b/OvmfPkg/RiscVVirt/README.md @@ -0,0 +1,46 @@ +# Support for RISC-V qemu virt platform + +## Overview +RISC-V qemu 'virt' is a generic platform which does not correspond to any real +hardware. + +EDK2 for RISC-V virt platform is a payload (S-mode) for a previous stage M-mode +firmware like opensbi. It follows PEI less design. + +The minimum qemu version required is +**[8.1](https://wiki.qemu.org/Planning/8.1)** or with commit +[7efd65423a](https://github.com/qemu/qemu/commit/7efd65423ab22e6f5890ca08ae40c84d6660242f) +which supports separate pflash devices for EDK2 code and variable storage. + +## Build + export WORKSPACE=`pwd` + export GCC5_RISCV64_PREFIX=riscv64-linux-gnu- + export PACKAGES_PATH=$WORKSPACE/edk2 + export EDK_TOOLS_PATH=$WORKSPACE/edk2/BaseTools + source edk2/edksetup.sh + make -C edk2/BaseTools + source edk2/edksetup.sh BaseTools + build -a RISCV64 --buildtarget RELEASE -p OvmfPkg/RiscVVirt/RiscVVirtQemu.dsc -t GCC5 + +## Test +1) RISC-V qemu pflash devices should be of of size 32MiB. + + `truncate -s 32M Build/RiscVVirtQemu/RELEASE_GCC5/FV/RISCV_VIRT_CODE.fd` + + `truncate -s 32M Build/RiscVVirtQemu/RELEASE_GCC5/FV/RISCV_VIRT_VARS.fd` + +2) Run qemu + + qemu-system-riscv64 \ + -accel tcg -m 4096 -smp 2 \ + -serial mon:stdio \ + -device virtio-gpu-pci -full-screen \ + -device qemu-xhci \ + -device usb-kbd \ + -blockdev node-name=pflash0,driver=file,read-only=on,filename=RISCV_VIRT_CODE.fd \ + -blockdev node-name=pflash1,driver=file,filename=RISCV_VIRT_VARS.fd \ + -M virt,pflash0=pflash0,pflash1=pflash1,acpi=off \ + -kernel linux/arch/riscv/boot/Image \ + -initrd buildroot/output/images/rootfs.cpio \ + -netdev user,id=net0 -device virtio-net-pci,netdev=net0 \ + -append "root=/dev/ram rw console=ttyS0 earlycon=uart8250,mmio,0x10000000" -- 2.34.1