From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pf1-f181.google.com (mail-pf1-f181.google.com [209.85.210.181]) by mx.groups.io with SMTP id smtpd.web11.6717.1687255378708199268 for ; Tue, 20 Jun 2023 03:02:58 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@ventanamicro.com header.s=google header.b=aTgV0He9; spf=pass (domain: ventanamicro.com, ip: 209.85.210.181, mailfrom: sunilvl@ventanamicro.com) Received: by mail-pf1-f181.google.com with SMTP id d2e1a72fcca58-666eba6f3d6so1675044b3a.3 for ; Tue, 20 Jun 2023 03:02:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1687255378; x=1689847378; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=LSaPrbl+WGW+ifZJqf2IzkTOPsz0bcy7KYr78CRiTCc=; b=aTgV0He9MZDXTlPOFCwqRH6dsLXEMgG0mHFThqu58X0SSrnhdBdwcOTGv9lMBoxupn mrckNXQtVvz8Z9TS7IJgAadk01hm9RVIJ/fyQNyxuVC+mBS5tHyZspC7hQ4RjjsSv8qv FZMZzT9l92IVq29Rf30czjV6QFZLrB2iKb4jDytlEsssxf8KWYJ7FDTbm1pqC+hXEfQD 7B5YVNud8cxpxrOV/Iqi5fIgnVemW2SnDRY2gL/olCj+sTbnfhJQYp77n3BoPo/IMv+Q c2i6s38LmeaUVbHOLzhMIdRTA3cIhq+3QnuSHi84LK5U1CsFuFlXv7oT7uV+2RSb0aI2 O1Aw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687255378; x=1689847378; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=LSaPrbl+WGW+ifZJqf2IzkTOPsz0bcy7KYr78CRiTCc=; b=bnWnHTtTpJmFcnDkXnioMI4s0RchcfrAT4WYVSZGtqcTwC21r9EZzWgGRawoapZ5IP n4Yj7NfOxs3SBx4YmXuCVOHNIkbPgAHlpumtI/IAmyLQikauIZ6I+tX0lIs/hZQG2MYa +q00ouPXGgM2d8DfalnZcqn5lunZQRVnVJw8dIAtXU/TVrfv1kp15gs13fDw0rGgfJuh pryLQMRoufTBS2+R0cHlB9Ka/hhDCcNvQVp+hqkdtNN/XxLl5qEUfxPm4xErTJrC5BBS iQiOYN2cftxNaQ+Arrek3Lth5JnYcLlffusggj4O6cFTErnyI9stvpePclscMpP3TYm8 TJ2Q== X-Gm-Message-State: AC+VfDy0pIevLYkDCUKnjF3RBV2/b9Fr12aMzR5zg1q4ecUNcfp7neuv BDul8Lq2w4UK89yYZ5Xg11Wk3kxqIcdUtqthW3g= X-Google-Smtp-Source: ACHHUZ73qhpA05XpTGKObrX/EcjEiLtLzcIjUYyxM4EsmCh/xwqkfXcUQbutqJ0G9zCxmtZUhdoQ7A== X-Received: by 2002:a05:6a20:4288:b0:11f:4412:fc77 with SMTP id o8-20020a056a20428800b0011f4412fc77mr2867831pzj.17.1687255377741; Tue, 20 Jun 2023 03:02:57 -0700 (PDT) Return-Path: Received: from kerodi.Dlink ([106.51.184.72]) by smtp.gmail.com with ESMTPSA id v14-20020aa7808e000000b00666b3b04758sm1033433pff.37.2023.06.20.03.02.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Jun 2023 03:02:57 -0700 (PDT) From: "Sunil V L" To: devel@edk2.groups.io Cc: Sunil V L , Ard Biesheuvel , Jiewen Yao , Jordan Justen , Gerd Hoffmann , Andrei Warkentin , Heinrich Schuchardt Subject: [PATCH v3 3/4] OvmfPkg/RiscVVirt: Add support for separate code and variable store Date: Tue, 20 Jun 2023 15:32:43 +0530 Message-Id: <20230620100244.1404606-4-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230620100244.1404606-1-sunilvl@ventanamicro.com> References: <20230620100244.1404606-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Currently, RiscVVirtQemu supports unified code and variable store mainly because only one pflash devices was available in qemu for EDK2. However, this doesn't allow to map the code part as read-only. With recent qemu enhancements, it is now possible for EDK2 to make use of both pflash devices in RISC-V virt machine. So, add support to create code and vars images separately. This also allows easy firmware code updates without losing the variable store. Signed-off-by: Sunil V L Cc: Ard Biesheuvel Cc: Jiewen Yao Cc: Jordan Justen Cc: Gerd Hoffmann Cc: Andrei Warkentin Cc: Heinrich Schuchardt --- OvmfPkg/RiscVVirt/RiscVVirtQemu.dsc | 2 +- OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf | 16 ++++++++++++---- OvmfPkg/RiscVVirt/RiscVVirt.fdf.inc | 14 ++++++-------- 3 files changed, 19 insertions(+), 13 deletions(-) diff --git a/OvmfPkg/RiscVVirt/RiscVVirtQemu.dsc b/OvmfPkg/RiscVVirt/RiscVVirtQemu.dsc index 414d186179fb..04573bc0f32e 100644 --- a/OvmfPkg/RiscVVirt/RiscVVirtQemu.dsc +++ b/OvmfPkg/RiscVVirt/RiscVVirtQemu.dsc @@ -85,7 +85,7 @@ [LibraryClasses.common] QemuLoadImageLib|OvmfPkg/Library/GenericQemuLoadImageLib/GenericQemuLoadImageLib.inf TimerLib|UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/BaseRiscV64CpuTimerLib.inf - VirtNorFlashPlatformLib|OvmfPkg/RiscVVirt/Library/VirtNorFlashPlatformLib/VirtNorFlashStaticLib.inf + VirtNorFlashPlatformLib|OvmfPkg/RiscVVirt/Library/VirtNorFlashPlatformLib/VirtNorFlashDeviceTreeLib.inf CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf diff --git a/OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf b/OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf index 354c9271d10c..21e4ba67379f 100644 --- a/OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf +++ b/OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf @@ -12,17 +12,25 @@ !include RiscVVirt.fdf.inc ################################################################################ -[FD.RISCV_VIRT] -BaseAddress = $(FW_BASE_ADDRESS)|gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFdBaseAddress -Size = $(FW_SIZE)|gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFirmwareFdSize +[FD.RISCV_VIRT_CODE] +BaseAddress = $(CODE_BASE_ADDRESS)|gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFdBaseAddress +Size = $(CODE_SIZE)|gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFirmwareFdSize ErasePolarity = 1 BlockSize = $(BLOCK_SIZE) -NumBlocks = $(FW_BLOCKS) +NumBlocks = $(CODE_BLOCKS) 0x00000000|$(CODE_SIZE) gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDxeMemFvBase|gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDxeMemFvSize FV = FVMAIN_COMPACT +################################################################################ +[FD.RISCV_VIRT_VARS] +BaseAddress = $(VARS_BASE_ADDRESS) +Size = $(VARS_SIZE) +ErasePolarity = 1 +BlockSize = $(VARS_BLOCK_SIZE) +NumBlocks = $(VARS_BLOCKS) + !include VarStore.fdf.inc ################################################################################ diff --git a/OvmfPkg/RiscVVirt/RiscVVirt.fdf.inc b/OvmfPkg/RiscVVirt/RiscVVirt.fdf.inc index b0a1c3293f33..eba612372fee 100644 --- a/OvmfPkg/RiscVVirt/RiscVVirt.fdf.inc +++ b/OvmfPkg/RiscVVirt/RiscVVirt.fdf.inc @@ -10,16 +10,14 @@ [Defines] DEFINE BLOCK_SIZE = 0x1000 +DEFINE PFLASH0_BASE = 0x20000000 DEFINE PFLASH1_BASE = 0x22000000 -DEFINE FW_BASE_ADDRESS = $(PFLASH1_BASE) -DEFINE FW_SIZE = 0x00800000 -DEFINE FW_BLOCKS = 0x800 - -DEFINE CODE_BASE_ADDRESS = $(FW_BASE_ADDRESS) -DEFINE CODE_SIZE = 0x00740000 -DEFINE CODE_BLOCKS = 0x740 +DEFINE CODE_BASE_ADDRESS = $(PFLASH0_BASE) +DEFINE CODE_SIZE = 0x00800000 +DEFINE CODE_BLOCKS = 0x800 +DEFINE VARS_BASE_ADDRESS = $(PFLASH1_BASE) DEFINE VARS_SIZE = 0x000C0000 DEFINE VARS_BLOCK_SIZE = 0x40000 DEFINE VARS_BLOCKS = 0x3 @@ -29,7 +27,7 @@ [Defines] # The total size of EFI Variable FD must include # all of sub regions of EFI Variable # -DEFINE VARS_OFFSET = $(CODE_SIZE) +DEFINE VARS_OFFSET = 0x00000000 DEFINE VARS_LIVE_SIZE = 0x00040000 DEFINE VARS_FTW_WORKING_OFFSET = $(VARS_OFFSET) + $(VARS_LIVE_SIZE) DEFINE VARS_FTW_WORKING_SIZE = 0x00040000 -- 2.34.1