From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mx.groups.io with SMTP id smtpd.web10.1392.1687316138004998774 for ; Tue, 20 Jun 2023 19:55:38 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=dNovcwEJ; spf=pass (domain: intel.com, ip: 134.134.136.20, mailfrom: ray.ni@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1687316138; x=1718852138; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=KF5itVnQHoW6YFsZFui1Y0fxzMJCnzgxyaUTy6TQwgg=; b=dNovcwEJNoy2zXIXCUWgbyDur7Wedqg6+nBcr7E75LCJQXD9brQVdQ3P bEEy0AYimVdvDBPTxUozJR+TilYNbdr8tRPInN2Nzbua7TbHUpys9w6YT qzlzUbYaU3aSHwpmJenjpsjBYiGNh2ukdce8pcCjQvbd4/po7iJmuniKR uhNwBEtt0tnLJk+jhnAIzRgQibGOYlzfbHL7dvL1OQLWetkmfUIZnwOai rhGCQbTzJOc9HuKBHSnFZ5khs5qBCuz/ERZ6LuYDlK4ucxW2ZohqHzipQ GbezDMeSlaWER5crZiAwmscXAhlCL0ybkHZZWf0qYGecpq/m+TPVrb/8t Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10747"; a="349777323" X-IronPort-AV: E=Sophos;i="6.00,259,1681196400"; d="scan'208";a="349777323" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jun 2023 19:55:37 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10747"; a="827253404" X-IronPort-AV: E=Sophos;i="6.00,259,1681196400"; d="scan'208";a="827253404" Received: from shwdeopenlab706.ccr.corp.intel.com ([10.239.55.95]) by fmsmga002.fm.intel.com with ESMTP; 20 Jun 2023 19:55:30 -0700 From: "Ni, Ray" To: devel@edk2.groups.io Cc: Eric Dong , Rahul Kumar , Gerd Hoffmann Subject: [PATCH v2 2/3] UefiCpuPkg/ResetVector: Add guidance of FDF ffs rule Date: Wed, 21 Jun 2023 10:55:21 +0800 Message-Id: <20230621025522.641-3-ray.ni@intel.com> X-Mailer: git-send-email 2.39.1.windows.1 In-Reply-To: <20230621025522.641-1-ray.ni@intel.com> References: <20230621025522.641-1-ray.ni@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable ResetVector assembly implementation puts "ALIGN 16" in the end to guarantee the final executable file size is multiple of 16 bytes. Because the module uses a special GUID which guarantees it's put in the very end of a FV, which should be also the end of the FD. All of these (file size is multiple of 16B, and the module is put at end of FV, FV is put at end of FD) guarantee the "JMP xxx" instruction is at FFFF_FFF0h. This patch updates INF file and ReadMe.txt to add guidance of FDF ffs rule for the ResetVector. Signed-off-by: Ray Ni Cc: Eric Dong Cc: Rahul Kumar Cc: Gerd Hoffmann Acked-by: Gerd Hoffmann --- UefiCpuPkg/ResetVector/Vtf0/ReadMe.txt | 27 +++++++------------------- UefiCpuPkg/ResetVector/Vtf0/Vtf0.inf | 19 +++++++++++++++++- 2 files changed, 25 insertions(+), 21 deletions(-) diff --git a/UefiCpuPkg/ResetVector/Vtf0/ReadMe.txt b/UefiCpuPkg/ResetVecto= r/Vtf0/ReadMe.txt index 97f4600968..4fcb15c3b1 100644 --- a/UefiCpuPkg/ResetVector/Vtf0/ReadMe.txt +++ b/UefiCpuPkg/ResetVector/Vtf0/ReadMe.txt @@ -1,15 +1,16 @@ =0D =3D=3D=3D HOW TO USE VTF0 =3D=3D=3D=0D +Add this line to your DSC [Components.IA32] or [Components.X64] section:=0D + UefiCpuPkg/ResetVector/Vtf0/ResetVector.inf=0D =0D Add this line to your FDF FV section:=0D -INF RuleOverride=3DRESET_VECTOR USE =3D IA32 UefiCpuPkg/ResetVector/Vtf0/= Bin/ResetVector.inf=0D -(For X64 SEC/PEI change IA32 to X64 =3D> 'USE =3D X64')=0D + INF RuleOverride=3DRESET_VECTOR UefiCpuPkg/ResetVector/Vtf0/ResetVector= .inf=0D =0D In your FDF FFS file rules sections add:=0D -[Rule.Common.SEC.RESET_VECTOR]=0D - FILE RAW =3D $(NAMED_GUID) {=0D - RAW RAW |.raw=0D - }=0D + [Rule.Common.SEC.RESET_VECTOR]=0D + FILE RAW =3D $(NAMED_GUID) {=0D + RAW BIN |.bin=0D + }=0D =0D =3D=3D=3D VTF0 Boot Flow =3D=3D=3D=0D =0D @@ -25,17 +26,3 @@ All inputs to SEC image are register based: EAX/RAX - Initial value of the EAX register (BIST: Built-in Self Test)=0D DI - 'BP': boot-strap processor, or 'AP': application processor=0D EBP/RBP - Pointer to the start of the Boot Firmware Volume=0D -=0D -=3D=3D=3D HOW TO BUILD VTF0 =3D=3D=3D=0D -=0D -Dependencies:=0D -* Python 3 or newer=0D -* Nasm 2.03 or newer=0D -=0D -To rebuild the VTF0 binaries:=0D -1. Change to VTF0 source dir: UefiCpuPkg/ResetVector/Vtf0=0D -2. nasm and python should be in executable path=0D -3. Run this command:=0D - python Build.py=0D -4. Binaries output will be in UefiCpuPkg/ResetVector/Vtf0/Bin=0D -=0D diff --git a/UefiCpuPkg/ResetVector/Vtf0/Vtf0.inf b/UefiCpuPkg/ResetVector/= Vtf0/Vtf0.inf index 9922cb2755..03d92d937f 100644 --- a/UefiCpuPkg/ResetVector/Vtf0/Vtf0.inf +++ b/UefiCpuPkg/ResetVector/Vtf0/Vtf0.inf @@ -1,7 +1,24 @@ ## @file=0D # Reset Vector=0D #=0D -# Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.
= =0D +# Note:=0D +# Conf/build_rule.txt contains the build rule [Nasm-to-Binary-Code-File= ]=0D +# to generate .bin file from .nasmb source.=0D +#=0D +# The platform FDF MUST have a FDF rule as follows to build the .bin=0D +# file as ResetVector .ffs file:=0D +#=0D +# [Rule.Common.SEC.RESET_VECTOR]=0D +# FILE RAW =3D $(NAMED_GUID) {=0D +# RAW BIN |.bin=0D +# }=0D +#=0D +# Following line in FDF forces to use the above rule for the ResetVecto= r:=0D +#=0D +# INF RuleOverride=3DRESET_VECTOR UefiCpuPkg/ResetVector/Vtf0/Vtf0.i= nf=0D +#=0D +#=0D +# Copyright (c) 2006 - 2023, Intel Corporation. All rights reserved.
= =0D #=0D # SPDX-License-Identifier: BSD-2-Clause-Patent=0D #=0D --=20 2.39.1.windows.1