From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pf1-f179.google.com (mail-pf1-f179.google.com [209.85.210.179]) by mx.groups.io with SMTP id smtpd.web10.6040.1687545668247954393 for ; Fri, 23 Jun 2023 11:41:08 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="signature has expired" header.i=@ventanamicro.com header.s=google header.b=f8vqxGkH; spf=pass (domain: ventanamicro.com, ip: 209.85.210.179, mailfrom: tphan@ventanamicro.com) Received: by mail-pf1-f179.google.com with SMTP id d2e1a72fcca58-668704a5b5bso757677b3a.0 for ; Fri, 23 Jun 2023 11:41:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1687545667; x=1690137667; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=2yq2ydKn7SUGk6ViMzCHbg0m2XJ2vh7HN55+Gc/lzkM=; b=f8vqxGkHxQjnalbmaDWZegAwmm94UAzdHcxN+c7nHSmQVTwsIkmK7Sd+fjirZPMBW4 S7Jx5iVuOk8uKDVphyvXdnuK8XmZer/t3pRwait/MNqNstHBYL2lmZHkKjLLzh1PhLBy pKN/yhP23CBjsPIl0ZR6GY6ikTJ0QKQVp/iK807eAwH91J7WmzPuwqmVAA6Pw4WHOQpC gYOAdZrIaIi5I7hniPOXB36GzD4KXER0K9agI97q2P9wYq64JNFvcSb23LNKPQJ0lBcW 5ZxYKj1bbsxX+htr1SmvTDgpB58G7Cue4zy5SZqqYiVRfLrF6MRwrrH3XWSqjNziZOV+ eEYQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687545667; x=1690137667; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=2yq2ydKn7SUGk6ViMzCHbg0m2XJ2vh7HN55+Gc/lzkM=; b=Y+yRGJKgCpx+4vx+mfAFZYiSsSdZXZbqZlFnJLTc3FgRQnbe7yqkzWBrZvVviLLQdb sXXoKGmSzVZj+SeYitAuK3sU1ve0Q/cIyxqDa91Mc2mQ9Z9Iq9ouV0wPsIn3ss5EChjE 3/2RaTQOJ/hK94x6VG22NmI5y+zK4rXEFDQIMbKd8gJ4Gz7SVKjnyTI4R7xdnalhkxY5 QVD/3kNjpqk7cbzUJ9Q4R+SEi382jciqerUuwjvn70B/x2H1NYkdxXzxjrF/ypKWaaZD zKHIpB45repzlg+8ymsZax6XUfAInWV/nPMxh1CorxT+0vl6B4xXt0Q1zFAaK2D7eiiS t+OQ== X-Gm-Message-State: AC+VfDyha/QkV1Z4thhv35RWkcsQCFBvTKGE07YU/hGjtyh1ZLyAB8NR nreqlcuYczZEuJMQC+1dYJ004EXFF854W8xtNW0T8Q== X-Google-Smtp-Source: ACHHUZ5Erztjkso8HOidWgq6j4ftWZ/csMhUjMU6SJ/u57LZJ9/pYEPD5v47jAORiD+dRu5agBxghg== X-Received: by 2002:a05:6a20:7290:b0:120:1baf:e56e with SMTP id o16-20020a056a20729000b001201bafe56emr20665089pzk.19.1687545667236; Fri, 23 Jun 2023 11:41:07 -0700 (PDT) Return-Path: Received: from localhost.localdomain (c-174-50-177-95.hsd1.ca.comcast.net. [174.50.177.95]) by smtp.gmail.com with ESMTPSA id v2-20020aa78502000000b006667b36e904sm6354184pfn.113.2023.06.23.11.41.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 Jun 2023 11:41:06 -0700 (PDT) From: "Tuan Phan" To: devel@edk2.groups.io Cc: michael.d.kinney@intel.com, gaoliming@byosoft.com.cn, zhiguang.liu@intel.com, sunilvl@ventanamicro.com, git@danielschaefer.me, andrei.warkentin@intel.com, ardb+tianocore@kernel.org, Tuan Phan Subject: [PATCH v4 0/7] RISC-V: Add MMU support Date: Fri, 23 Jun 2023 11:39:27 -0700 Message-Id: <20230623183934.23905-1-tphan@ventanamicro.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit This series adds MMU support for RISC-V. Only SV39/48/57 modes are supported and tested. The MMU is required to support setting page attribute which is the first basic step to support security booting on RISC-V. There are two parts: 1. Add MMU base library. MMU will be enabled during CpuDxe initialization. 2. Fix all resources should be populated in HOB or added to GCD by driver before accessing when MMU enabled. All changes can be found in the branch tphan/riscv_mmu at: https://github.com/pttuan/edk2.git Changes in v4: - Rebased master. - Added VirtNorFlashDxe to APRIORI DXE list. Changes in v3: - Move MMU library to UefiCpuPkg. - Add Andrei reviewed-by. Changes in v2: - Move MMU core to a library. - Setup SATP mode as highest possible that HW supports. Tuan Phan (7): MdePkg/BaseLib: RISC-V: Support getting satp register value MdePkg/Register: RISC-V: Add satp mode bits shift definition OvmfPkg/RiscVVirt: VirtNorFlashPlatformLib: Fix wrong flash size OvmfPkg/RiscVVirt: SEC: Add IO memory resource hob for platform devices OvmfPkg/RiscVVirt: Add VirtNorFlashDxe to APRIORI list OvmfPkg: RiscVVirt: Remove satp bare mode setting UefiCpuPkg: RISC-V: Support MMU with SV39/48/57 mode MdePkg/Include/Library/BaseLib.h | 5 + .../Include/Register/RiscV64/RiscVEncoding.h | 7 +- MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S | 8 + .../VirtNorFlashStaticLib.c | 3 +- OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc | 1 + OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf | 10 + OvmfPkg/RiscVVirt/Sec/Memory.c | 18 +- OvmfPkg/RiscVVirt/Sec/Platform.c | 62 ++ UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c | 9 +- UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h | 2 + UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf | 2 + UefiCpuPkg/Include/Library/BaseRiscVMmuLib.h | 39 ++ .../Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c | 569 ++++++++++++++++++ .../BaseRiscVMmuLib/BaseRiscVMmuLib.inf | 26 + .../Library/BaseRiscVMmuLib/RiscVMmuCore.S | 31 + 15 files changed, 770 insertions(+), 22 deletions(-) create mode 100644 UefiCpuPkg/Include/Library/BaseRiscVMmuLib.h create mode 100644 UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c create mode 100644 UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf create mode 100644 UefiCpuPkg/Library/BaseRiscVMmuLib/RiscVMmuCore.S -- 2.25.1