public inbox for devel@edk2.groups.io
 help / color / mirror / Atom feed
From: "Tuan Phan" <tphan@ventanamicro.com>
To: devel@edk2.groups.io
Cc: michael.d.kinney@intel.com, gaoliming@byosoft.com.cn,
	zhiguang.liu@intel.com, sunilvl@ventanamicro.com,
	git@danielschaefer.me, andrei.warkentin@intel.com,
	ardb+tianocore@kernel.org, Tuan Phan <tphan@ventanamicro.com>
Subject: [PATCH v4 2/7] MdePkg/Register: RISC-V: Add satp mode bits shift definition
Date: Fri, 23 Jun 2023 11:39:29 -0700	[thread overview]
Message-ID: <20230623183934.23905-3-tphan@ventanamicro.com> (raw)
In-Reply-To: <20230623183934.23905-1-tphan@ventanamicro.com>

The satp mode bits shift is used cross modules. It should be defined
in one place.

Signed-off-by: Tuan Phan <tphan@ventanamicro.com>
Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
---
 MdePkg/Include/Register/RiscV64/RiscVEncoding.h | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/MdePkg/Include/Register/RiscV64/RiscVEncoding.h b/MdePkg/Include/Register/RiscV64/RiscVEncoding.h
index 5c2989b797bf..2bde8db478ff 100644
--- a/MdePkg/Include/Register/RiscV64/RiscVEncoding.h
+++ b/MdePkg/Include/Register/RiscV64/RiscVEncoding.h
@@ -58,9 +58,10 @@
 #define PRV_S  1UL
 #define PRV_M  3UL
 
-#define SATP64_MODE  0xF000000000000000ULL
-#define SATP64_ASID  0x0FFFF00000000000ULL
-#define SATP64_PPN   0x00000FFFFFFFFFFFULL
+#define SATP64_MODE        0xF000000000000000ULL
+#define SATP64_MODE_SHIFT  60
+#define SATP64_ASID        0x0FFFF00000000000ULL
+#define SATP64_PPN         0x00000FFFFFFFFFFFULL
 
 #define SATP_MODE_OFF   0UL
 #define SATP_MODE_SV32  1UL
-- 
2.25.1


  parent reply	other threads:[~2023-06-23 18:41 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-06-23 18:39 [PATCH v4 0/7] RISC-V: Add MMU support Tuan Phan
2023-06-23 18:39 ` [PATCH v4 1/7] MdePkg/BaseLib: RISC-V: Support getting satp register value Tuan Phan
2023-06-23 18:39 ` Tuan Phan [this message]
2023-06-27 20:10   ` [PATCH v4 2/7] MdePkg/Register: RISC-V: Add satp mode bits shift definition Michael D Kinney
2023-06-23 18:39 ` [PATCH v4 3/7] OvmfPkg/RiscVVirt: VirtNorFlashPlatformLib: Fix wrong flash size Tuan Phan
2023-06-23 18:39 ` [PATCH v4 4/7] OvmfPkg/RiscVVirt: SEC: Add IO memory resource hob for platform devices Tuan Phan
2023-06-23 18:39 ` [PATCH v4 5/7] OvmfPkg/RiscVVirt: Add VirtNorFlashDxe to APRIORI list Tuan Phan
2023-06-28 16:47   ` Sunil V L
2023-06-28 21:27     ` Tuan Phan
2023-07-04  5:07       ` Sunil V L
2023-07-04  6:45         ` Tuan Phan
2023-07-04  7:01           ` Sunil V L
2023-07-13 19:08             ` Tuan Phan
2023-07-14  4:19               ` Sunil V L
2023-06-23 18:39 ` [PATCH v4 6/7] OvmfPkg: RiscVVirt: Remove satp bare mode setting Tuan Phan
2023-06-23 18:39 ` [PATCH v4 7/7] UefiCpuPkg: RISC-V: Support MMU with SV39/48/57 mode Tuan Phan
2023-07-14 10:24   ` Sunil V L
2023-07-14 19:10     ` Tuan Phan
2023-06-25  8:45 ` [edk2-devel] UsbNetworkPkg not find in UDK 202305 stable version Yoshinoya
2023-07-15  5:21 ` [PATCH v4 0/7] RISC-V: Add MMU support Sunil V L

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-list from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20230623183934.23905-3-tphan@ventanamicro.com \
    --to=devel@edk2.groups.io \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox