From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pf1-f176.google.com (mail-pf1-f176.google.com [209.85.210.176]) by mx.groups.io with SMTP id smtpd.web11.6112.1687545670860183710 for ; Fri, 23 Jun 2023 11:41:10 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@ventanamicro.com header.s=google header.b=YuXMWaoM; spf=pass (domain: ventanamicro.com, ip: 209.85.210.176, mailfrom: tphan@ventanamicro.com) Received: by mail-pf1-f176.google.com with SMTP id d2e1a72fcca58-666eec46206so689768b3a.3 for ; Fri, 23 Jun 2023 11:41:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1687545670; x=1690137670; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=HGi/4W0sKDcGBCxIqQ5a9gGaAcEsiQRUbEnx+V0s4bQ=; b=YuXMWaoMbbVAn7LKUfqiYUoCvBXXXUJMMUJ2H0HXq0g76WngDWmXXLjJ8Ek8NoleZh n1Z0M3+zOjO10xb1REP31mn8sNAe90n9k42nTCQI82NDHNH03rnODIEXOWmwhGNrgLCz gy3Rud74gG+Nby53eJwkFkW+jUwurCdE7j4SjzZ8tk1tSI/mtKyxkoDz1qGJpz8/CE/H 3OxnMvxs9Ohu2bK3/JUyyW9y2or4EVc6C6yRgalNsv5ngUiP+V90FyEiECtvNsmRzwN2 V5u/kjcmjMQQj7WAu1kuS4FMWyj4V1fnp9NAV8GGqEBnpbZQLQKaZQWo3PrUEn00Ap3y XRkQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687545670; x=1690137670; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HGi/4W0sKDcGBCxIqQ5a9gGaAcEsiQRUbEnx+V0s4bQ=; b=jcvQrVc2K9NlNHXqpVWTYp8e0IVkcUt7aOK4k9dPbtrNAoy3YihJ1/DbdOuOHm5mVb FZHUq823hzu9TYwhsCQdvqXc47o6YtVQiHK6saToFGRRaSTrKbuqmP899dtzb9+NVGBF TiVyZJnv/TvIO+DyOChFcnzPNtLEBPcGXzDf/nPO12bKfJOfT6xNgjjitv0/ns5a95SJ syz3sqS9RTKrSwyaJrMtlqwdcSIq2wEAhQo43C1hFw/rsWepE4ArREBYJZlTIj/y7Nlq WfLCwrM+JBSYsxU/30kaPVBAuZq3nwFwQ0pw4cLHL61bIut33fEVx63jQ/LeZM2fA3IB eULQ== X-Gm-Message-State: AC+VfDx8oEUHTmcfjZwL+ZAtr7kB92QOkWWtEWygvFaobtq0+CR4Ht1t eUvTXojRHOd/eXIaLnVTxt4sEWQfMcKVNWUOMSRhIw== X-Google-Smtp-Source: ACHHUZ4vmEHzoD12G7RF6qGPBmxUJTRL3eMycd8qQE/NEQIpkUA9NRLdUofCycWGsH3IVsL8p+Prdg== X-Received: by 2002:a05:6a00:b44:b0:668:79d6:34df with SMTP id p4-20020a056a000b4400b0066879d634dfmr19546797pfo.23.1687545669931; Fri, 23 Jun 2023 11:41:09 -0700 (PDT) Return-Path: Received: from localhost.localdomain (c-174-50-177-95.hsd1.ca.comcast.net. [174.50.177.95]) by smtp.gmail.com with ESMTPSA id v2-20020aa78502000000b006667b36e904sm6354184pfn.113.2023.06.23.11.41.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 Jun 2023 11:41:09 -0700 (PDT) From: "Tuan Phan" To: devel@edk2.groups.io Cc: michael.d.kinney@intel.com, gaoliming@byosoft.com.cn, zhiguang.liu@intel.com, sunilvl@ventanamicro.com, git@danielschaefer.me, andrei.warkentin@intel.com, ardb+tianocore@kernel.org, Tuan Phan Subject: [PATCH v4 2/7] MdePkg/Register: RISC-V: Add satp mode bits shift definition Date: Fri, 23 Jun 2023 11:39:29 -0700 Message-Id: <20230623183934.23905-3-tphan@ventanamicro.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230623183934.23905-1-tphan@ventanamicro.com> References: <20230623183934.23905-1-tphan@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable The satp mode bits shift is used cross modules. It should be defined in one place. Signed-off-by: Tuan Phan Reviewed-by: Andrei Warkentin Reviewed-by: Sunil V L --- MdePkg/Include/Register/RiscV64/RiscVEncoding.h | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/MdePkg/Include/Register/RiscV64/RiscVEncoding.h b/MdePkg/Inclu= de/Register/RiscV64/RiscVEncoding.h index 5c2989b797bf..2bde8db478ff 100644 --- a/MdePkg/Include/Register/RiscV64/RiscVEncoding.h +++ b/MdePkg/Include/Register/RiscV64/RiscVEncoding.h @@ -58,9 +58,10 @@ #define PRV_S 1UL=0D #define PRV_M 3UL=0D =0D -#define SATP64_MODE 0xF000000000000000ULL=0D -#define SATP64_ASID 0x0FFFF00000000000ULL=0D -#define SATP64_PPN 0x00000FFFFFFFFFFFULL=0D +#define SATP64_MODE 0xF000000000000000ULL=0D +#define SATP64_MODE_SHIFT 60=0D +#define SATP64_ASID 0x0FFFF00000000000ULL=0D +#define SATP64_PPN 0x00000FFFFFFFFFFFULL=0D =0D #define SATP_MODE_OFF 0UL=0D #define SATP_MODE_SV32 1UL=0D --=20 2.25.1