From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pl1-f173.google.com (mail-pl1-f173.google.com [209.85.214.173]) by mx.groups.io with SMTP id smtpd.web10.22610.1688371727751801895 for ; Mon, 03 Jul 2023 01:08:47 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@ventanamicro.com header.s=google header.b=pmIHTkhc; spf=pass (domain: ventanamicro.com, ip: 209.85.214.173, mailfrom: sunilvl@ventanamicro.com) Received: by mail-pl1-f173.google.com with SMTP id d9443c01a7336-1b852785a65so25756205ad.0 for ; Mon, 03 Jul 2023 01:08:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1688371727; x=1690963727; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=PRQmxp4nniDpUX6Q4pGIt95f5p4XJ/+4lGb1hrTBNWo=; b=pmIHTkhcKtPa44uBmL4wpzZbG0WShYLwyIUSkIZEz45Yl6Am0FQx2mG6C04SBHwiLv Vl1WttLszODiCQ+44alLiOftXBrlFbC5d248VDnkxIzjA6h5iK/qdznrDdzOrOVxWcLw RBl7Qi1ABy9ZQqHYEUb8dWU82gQDFFnOznfnkpVSlLpBe9bKS74Gf3OwQU48+6JkibZX Mwl28qmAFMtI0v54YqRdnkW55XCH5RcFBGTNTPXhyQLh1ORUJdapj4iFSiwdljg2ev2E nlu3eE8tMXDW5moeXx7+CTaDymaQOb6CKld3kQmA5XgAEph2bsY6vlnRLp5k5x/uHJzm HjKw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688371727; x=1690963727; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PRQmxp4nniDpUX6Q4pGIt95f5p4XJ/+4lGb1hrTBNWo=; b=BnZuykLvZ2fMCzy/SUsDAPVA38UoLziGue1AObE7IHRpZPiHe1i1rgf94PwRzpHkgG Jnq1WkJfbqDcKJsxep51S1aMaPz+h3CECuWRaZyIABLJpLxYoIS6IHPmcrX0nkSBwGnd u/PY596LIhyuLJiW3XH+34LvhJCoC5ZFTM/NqoLZmm7zBnGSE4W7NauyC4vL16cpTxa/ uqtzy2lezFg9eyeqwNdKo/Flma14pcv3898u8VOfl3B9Jab3kwroK3HBu3muFHSrLSB8 24O/vMMhHK+vcWcAKeEo8zHeeNI/cqsTv4oqNvQmv00aG73BfdXDPI9H5XRa0hxxJBIi qyRA== X-Gm-Message-State: AC+VfDwKgj3AIipskngPDR76XrA93GBLFne3BQjFvhCFDOZN77PWCp5D HUgGs5DQpUpFH6Hs9dPW+/qM8Kj8/yuzPJQurCA= X-Google-Smtp-Source: ACHHUZ5bPty1rEDep43U36KgtBQGFd5bJvxJtJCRkg3W0cSDw4XBZNuvx1CbVFSi+b+5kzttwaSlqA== X-Received: by 2002:a17:902:cecb:b0:1b7:dfbd:4dd3 with SMTP id d11-20020a170902cecb00b001b7dfbd4dd3mr23615495plg.9.1688371726933; Mon, 03 Jul 2023 01:08:46 -0700 (PDT) Return-Path: Received: from sunil-laptop.. ([106.51.184.72]) by smtp.gmail.com with ESMTPSA id s18-20020a17090a881200b0024e05b7ba8bsm14863253pjn.25.2023.07.03.01.08.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Jul 2023 01:08:46 -0700 (PDT) From: "Sunil V L" To: devel@edk2.groups.io Cc: Sunil V L , Rebecca Cran , Liming Gao , Bob Feng , Yuwei Chen , Ard Biesheuvel Subject: [PATCH 3/4] BaseTools/tools_def: Add CLANGDWARF support for RISC-V Date: Mon, 3 Jul 2023 13:38:30 +0530 Message-Id: <20230703080831.51075-4-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230703080831.51075-1-sunilvl@ventanamicro.com> References: <20230703080831.51075-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4478 Add tools_def definitions to support CLANGDWARF toolchain for RISC-V. This uses clang and the llvm LLD linker. This helps people by not requiring to install multiple cross compilers for different architectures. Cc: Rebecca Cran Cc: Liming Gao Cc: Bob Feng Cc: Yuwei Chen Cc: Ard Biesheuvel Signed-off-by: Sunil V L --- BaseTools/Conf/tools_def.template | 52 +++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/BaseTools/Conf/tools_def.template b/BaseTools/Conf/tools_def.template index 90f4105506e5..47d8c379d9f2 100755 --- a/BaseTools/Conf/tools_def.template +++ b/BaseTools/Conf/tools_def.template @@ -745,6 +745,7 @@ DEFINE GCC_LOONGARCH64_CC_FLAGS = DEF(GCC_ALL_CC_FLAGS) -mabi=lp64d -fno-asyn DEFINE GCC_ARM_CC_XIPFLAGS = -mno-unaligned-access DEFINE GCC_AARCH64_CC_FLAGS = DEF(GCC_ALL_CC_FLAGS) -mlittle-endian -fno-short-enums -fverbose-asm -funsigned-char -ffunction-sections -fdata-sections -Wno-address -fno-asynchronous-unwind-tables -fno-unwind-tables -fno-pic -fno-pie -ffixed-x18 DEFINE GCC_AARCH64_CC_XIPFLAGS = -mstrict-align -mgeneral-regs-only +DEFINE GCC_RISCV64_CC_XIPFLAGS = -mstrict-align -mgeneral-regs-only DEFINE GCC_DLINK_FLAGS_COMMON = -nostdlib --pie DEFINE GCC_DLINK2_FLAGS_COMMON = -Wl,--script=$(EDK_TOOLS_PATH)/Scripts/GccBase.lds DEFINE GCC_IA32_X64_DLINK_COMMON = DEF(GCC_DLINK_FLAGS_COMMON) --gc-sections @@ -2023,6 +2024,57 @@ DEFINE CLANGDWARF_AARCH64_DLINK_FLAGS = DEF(CLANGDWARF_AARCH64_TARGET) DEF(GCC_ RELEASE_CLANGDWARF_AARCH64_CC_FLAGS = DEF(CLANGDWARF_AARCH64_CC_FLAGS) $(PLATFORM_FLAGS) -flto -O3 RELEASE_CLANGDWARF_AARCH64_DLINK_FLAGS = DEF(CLANGDWARF_AARCH64_DLINK_FLAGS) -flto -Wl,-O3 -fuse-ld=lld -L$(WORKSPACE)/ArmPkg/Library/GccLto -llto-aarch64 -Wl,-plugin-opt=-pass-through=-llto-aarch64 -Wl,--no-pie,--no-relax +################## +# CLANGDWARF RISCV64 definitions +################## +DEFINE CLANGDWARF_RISCV64_TARGET = -target riscv64-linux-gnu +DEFINE CLANGDWARF_RISCV64_CC_FLAGS = DEF(GCC5_RISCV64_CC_FLAGS) DEF(CLANGDWARF_RISCV64_TARGET) DEF(CLANGDWARF_WARNING_OVERRIDES) + +# This is similar to GCC flags but without -n +DEFINE CLANGDWARF_RISCV64_ALL_DLINK_COMMON = -nostdlib -Wl,-q,--gc-sections -z common-page-size=0x40 +DEFINE CLANGDWARF_RISCV64_ALL_DLINK_FLAGS = DEF(CLANGDWARF_RISCV64_ALL_DLINK_COMMON) -Wl,--entry,$(IMAGE_ENTRY_POINT) -u $(IMAGE_ENTRY_POINT) -Wl,-Map,$(DEST_DIR_DEBUG)/$(BASE_NAME).map +DEFINE CLANGDWARF_RISCV64_DLINK_FLAGS = DEF(CLANGDWARF_RISCV64_TARGET) DEF(CLANGDWARF_RISCV64_ALL_DLINK_FLAGS) -Wl,-melf64lriscv,--oformat=elf64-littleriscv,--no-relax + +*_CLANGDWARF_RISCV64_PP_FLAGS = DEF(GCC_PP_FLAGS) +*_CLANGDWARF_RISCV64_ASLCC_FLAGS = DEF(GCC_ASLCC_FLAGS) +*_CLANGDWARF_RISCV64_APP_FLAGS = +*_CLANGDWARF_RISCV64_ASL_FLAGS = DEF(IASL_FLAGS) +*_CLANGDWARF_RISCV64_ASL_OUTFLAGS = DEF(IASL_OUTFLAGS) +*_CLANGDWARF_RISCV64_DTCPP_FLAGS = DEF(GCC_DTCPP_FLAGS) +*_CLANGDWARF_RISCV64_DEPS_FLAGS = DEF(GCC_DEPS_FLAGS) + +*_CLANGDWARF_RISCV64_CC_PATH = ENV(CLANGDWARF_BIN)clang +*_CLANGDWARF_RISCV64_ASM_PATH = ENV(CLANGDWARF_BIN)clang +*_CLANGDWARF_RISCV64_PP_PATH = ENV(CLANGDWARF_BIN)clang +*_CLANGDWARF_RISCV64_VFRPP_PATH = ENV(CLANGDWARF_BIN)clang +*_CLANGDWARF_RISCV64_ASLCC_PATH = ENV(CLANGDWARF_BIN)clang +*_CLANGDWARF_RISCV64_ASLPP_PATH = ENV(CLANGDWARF_BIN)clang +*_CLANGDWARF_RISCV64_DLINK_PATH = ENV(CLANGDWARF_BIN)clang +*_CLANGDWARF_RISCV64_ASLDLINK_PATH = ENV(CLANGDWARF_BIN)clang + +*_CLANGDWARF_RISCV64_SLINK_PATH = ENV(CLANGDWARF_BIN)llvm-ar +*_CLANGDWARF_RISCV64_RC_PATH = ENV(CLANGDWARF_BIN)llvm-objcopy + +*_CLANGDWARF_RISCV64_ASLCC_FLAGS = DEF(GCC_ASLCC_FLAGS) -flto +*_CLANGDWARF_RISCV64_ASLDLINK_FLAGS = DEF(CLANGDWARF_RISCV64_TARGET) DEF(GCC5_RISCV32_RISCV64_ASLDLINK_FLAGS) +*_CLANGDWARF_RISCV64_ASM_FLAGS = DEF(GCC_ASM_FLAGS) DEF(CLANGDWARF_RISCV64_TARGET) $(PLATFORM_FLAGS) -Qunused-arguments -mabi=lp64 -mno-relax -flto +*_CLANGDWARF_RISCV64_DLINK_FLAGS = DEF(CLANGDWARF_RISCV64_TARGET) DEF(GCC5_RISCV64_DLINK_FLAGS) +*_CLANGDWARF_RISCV64_DLINK_XIPFLAGS = -z common-page-size=0x20 +*_CLANGDWARF_RISCV64_DLINK2_FLAGS = DEF(GCC_DLINK2_FLAGS_COMMON) -Wl,--defsym=PECOFF_HEADER_SIZE=0x240 +*_CLANGDWARF_RISCV64_PLATFORM_FLAGS = +*_CLANGDWARF_RISCV64_PP_FLAGS = DEF(GCC_PP_FLAGS) DEF(CLANGDWARF_RISCV64_TARGET) $(PLATFORM_FLAGS) +*_CLANGDWARF_RISCV64_RC_FLAGS = DEF(GCC_RISCV64_RC_FLAGS) +*_CLANGDWARF_RISCV64_VFRPP_FLAGS = DEF(GCC_VFRPP_FLAGS) DEF(CLANGDWARF_RISCV64_TARGET) $(PLATFORM_FLAGS) +*_CLANGDWARF_RISCV64_ASLPP_FLAGS = DEF(GCC_ASLPP_FLAGS) DEF(CLANGDWARF_RISCV64_TARGET) +*_CLANGDWARF_RISCV64_CC_XIPFLAGS = DEF(GCC_RISCV64_CC_XIPFLAGS) + + DEBUG_CLANGDWARF_RISCV64_CC_FLAGS = DEF(CLANGDWARF_RISCV64_CC_FLAGS) $(PLATFORM_FLAGS) -flto -O1 + DEBUG_CLANGDWARF_RISCV64_DLINK_FLAGS = DEF(CLANGDWARF_RISCV64_DLINK_FLAGS) -flto -Wl,-O1 -fuse-ld=lld -Wl,--no-pie,--no-relax + NOOPT_CLANGDWARF_RISCV64_CC_FLAGS = DEF(CLANGDWARF_RISCV64_CC_FLAGS) $(PLATFORM_FLAGS) -O0 + NOOPT_CLANGDWARF_RISCV64_DLINK_FLAGS = DEF(CLANGDWARF_RISCV64_DLINK_FLAGS) -fuse-ld=lld -Wl,--no-pie,--no-relax +RELEASE_CLANGDWARF_RISCV64_CC_FLAGS = DEF(CLANGDWARF_RISCV64_CC_FLAGS) $(PLATFORM_FLAGS) -flto -O3 +RELEASE_CLANGDWARF_RISCV64_DLINK_FLAGS = DEF(CLANGDWARF_RISCV64_DLINK_FLAGS) -flto -Wl,-O3 -fuse-ld=lld -Wl,--no-pie,--no-relax + # # # XCODE5 support -- 2.34.1