* [PATCH 1/4] OvmfPkg/RiscVVirt: use 'auto' alignment and FIXED for XIP modules
2023-07-03 8:08 [PATCH 0/4] OvmfPkg/RiscVVirt: Add CLANGDWARF toolchain support Sunil V L
@ 2023-07-03 8:08 ` Sunil V L
2023-07-03 8:08 ` [PATCH 2/4] OvmfPkg/RiscVVirt: SecEntry: Remove unnecessary assembly directives Sunil V L
` (3 subsequent siblings)
4 siblings, 0 replies; 8+ messages in thread
From: Sunil V L @ 2023-07-03 8:08 UTC (permalink / raw)
To: devel
Cc: Sunil V L, Ard Biesheuvel, Jiewen Yao, Jordan Justen,
Andrei Warkentin
Use auto alignment and FIXED FFS attribute for XIP modules similar
to [1]. Without this change, the CLANGDWARF toolchain will fail to
build with below error.
GenFfs: ERROR 1000: Unknown option
SectionAlign option must be specified with section file.
[1] - https://github.com/tianocore/edk2/commit/7669f7349829f0e4755552ba0d6e600492fd8170
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc Gerd Hoffmann <kraxel@redhat.com>
Cc: Andrei Warkentin <andrei.warkentin@intel.com>
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
---
OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf | 34 +++++++++--------------------
1 file changed, 10 insertions(+), 24 deletions(-)
diff --git a/OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf b/OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf
index 21e4ba67379f..b5aebfae078c 100644
--- a/OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf
+++ b/OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf
@@ -240,30 +240,15 @@ [FV.FVMAIN_COMPACT]
}
[Rule.Common.SEC]
- FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
- PE32 PE32 Align=4K $(INF_OUTPUT)/$(MODULE_NAME).efi
+ FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED FIXED {
+ PE32 PE32 Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi
UI STRING ="$(MODULE_NAME)" Optional
VERSION STRING ="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
}
-[Rule.Common.PEI_CORE]
- FILE PEI_CORE = $(NAMED_GUID) {
- PE32 PE32 Align=4K $(INF_OUTPUT)/$(MODULE_NAME).efi
- UI STRING ="$(MODULE_NAME)" Optional
- VERSION STRING ="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
- }
-
-[Rule.Common.PEIM]
- FILE PEIM = $(NAMED_GUID) {
- PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
- PE32 PE32 Align=4K $(INF_OUTPUT)/$(MODULE_NAME).efi
- UI STRING="$(MODULE_NAME)" Optional
- VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
- }
-
[Rule.Common.DXE_CORE]
FILE DXE_CORE = $(NAMED_GUID) {
- PE32 PE32 Align=4K $(INF_OUTPUT)/$(MODULE_NAME).efi
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
UI STRING="$(MODULE_NAME)" Optional
VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
}
@@ -271,7 +256,7 @@ [Rule.Common.DXE_CORE]
[Rule.Common.DXE_DRIVER]
FILE DRIVER = $(NAMED_GUID) {
DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
- PE32 PE32 Align=4K $(INF_OUTPUT)/$(MODULE_NAME).efi
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
UI STRING="$(MODULE_NAME)" Optional
VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
}
@@ -279,7 +264,7 @@ [Rule.Common.DXE_DRIVER]
[Rule.Common.DXE_RUNTIME_DRIVER]
FILE DRIVER = $(NAMED_GUID) {
DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
- PE32 PE32 Align = 4K $(INF_OUTPUT)/$(MODULE_NAME).efi
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
UI STRING="$(MODULE_NAME)" Optional
VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
}
@@ -287,7 +272,7 @@ [Rule.Common.DXE_RUNTIME_DRIVER]
[Rule.Common.UEFI_DRIVER]
FILE DRIVER = $(NAMED_GUID) {
DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
- PE32 PE32 Align=4K $(INF_OUTPUT)/$(MODULE_NAME).efi
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
UI STRING="$(MODULE_NAME)" Optional
VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
}
@@ -295,21 +280,21 @@ [Rule.Common.UEFI_DRIVER]
[Rule.Common.UEFI_DRIVER.BINARY]
FILE DRIVER = $(NAMED_GUID) {
DXE_DEPEX DXE_DEPEX Optional |.depex
- PE32 PE32 Align=4K |.efi
+ PE32 PE32 |.efi
UI STRING="$(MODULE_NAME)" Optional
VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
}
[Rule.Common.UEFI_APPLICATION]
FILE APPLICATION = $(NAMED_GUID) {
- PE32 PE32 Align=4K $(INF_OUTPUT)/$(MODULE_NAME).efi
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
UI STRING="$(MODULE_NAME)" Optional
VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
}
[Rule.Common.UEFI_APPLICATION.BINARY]
FILE APPLICATION = $(NAMED_GUID) {
- PE32 PE32 Align=4K |.efi
+ PE32 PE32 |.efi
UI STRING="$(MODULE_NAME)" Optional
VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
}
@@ -318,4 +303,5 @@ [Rule.Common.USER_DEFINED.ACPITABLE]
FILE FREEFORM = $(NAMED_GUID) {
RAW ACPI |.acpi
RAW ASL |.aml
+ UI STRING="$(MODULE_NAME)" Optional
}
--
2.34.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH 2/4] OvmfPkg/RiscVVirt: SecEntry: Remove unnecessary assembly directives
2023-07-03 8:08 [PATCH 0/4] OvmfPkg/RiscVVirt: Add CLANGDWARF toolchain support Sunil V L
2023-07-03 8:08 ` [PATCH 1/4] OvmfPkg/RiscVVirt: use 'auto' alignment and FIXED for XIP modules Sunil V L
@ 2023-07-03 8:08 ` Sunil V L
2023-07-03 8:08 ` [PATCH 3/4] BaseTools/tools_def: Add CLANGDWARF support for RISC-V Sunil V L
` (2 subsequent siblings)
4 siblings, 0 replies; 8+ messages in thread
From: Sunil V L @ 2023-07-03 8:08 UTC (permalink / raw)
To: devel
Cc: Sunil V L, Ard Biesheuvel, Jiewen Yao, Jordan Justen,
Gerd Hoffmann, Andrei Warkentin
llvm fails to resolve _ModuleEntry when these extra directives are
present. ASM_FUNC already takes care what is required.
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Andrei Warkentin <andrei.warkentin@intel.com>
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
---
OvmfPkg/RiscVVirt/Sec/SecEntry.S | 3 ---
1 file changed, 3 deletions(-)
diff --git a/OvmfPkg/RiscVVirt/Sec/SecEntry.S b/OvmfPkg/RiscVVirt/Sec/SecEntry.S
index e919a3cb0e80..192fff321ce5 100644
--- a/OvmfPkg/RiscVVirt/Sec/SecEntry.S
+++ b/OvmfPkg/RiscVVirt/Sec/SecEntry.S
@@ -7,9 +7,6 @@
#include "SecMain.h"
-.text
-.align 3
-
ASM_FUNC (_ModuleEntryPoint)
/* Use Temp memory as the stack for calling to C code */
li a4, FixedPcdGet32 (PcdOvmfSecPeiTempRamBase)
--
2.34.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH 3/4] BaseTools/tools_def: Add CLANGDWARF support for RISC-V
2023-07-03 8:08 [PATCH 0/4] OvmfPkg/RiscVVirt: Add CLANGDWARF toolchain support Sunil V L
2023-07-03 8:08 ` [PATCH 1/4] OvmfPkg/RiscVVirt: use 'auto' alignment and FIXED for XIP modules Sunil V L
2023-07-03 8:08 ` [PATCH 2/4] OvmfPkg/RiscVVirt: SecEntry: Remove unnecessary assembly directives Sunil V L
@ 2023-07-03 8:08 ` Sunil V L
2023-07-10 1:52 ` 回复: " gaoliming
2023-07-03 8:08 ` [PATCH 4/4] OvmfPkg/RiscVVirt: Update README for CLANGDWARF support Sunil V L
2023-07-03 12:15 ` [PATCH 0/4] OvmfPkg/RiscVVirt: Add CLANGDWARF toolchain support Ard Biesheuvel
4 siblings, 1 reply; 8+ messages in thread
From: Sunil V L @ 2023-07-03 8:08 UTC (permalink / raw)
To: devel
Cc: Sunil V L, Rebecca Cran, Liming Gao, Bob Feng, Yuwei Chen,
Ard Biesheuvel
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4478
Add tools_def definitions to support CLANGDWARF toolchain
for RISC-V. This uses clang and the llvm LLD linker. This
helps people by not requiring to install multiple
cross compilers for different architectures.
Cc: Rebecca Cran <rebecca@bsdio.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Yuwei Chen <yuwei.chen@intel.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
---
BaseTools/Conf/tools_def.template | 52 +++++++++++++++++++++++++++++++
1 file changed, 52 insertions(+)
diff --git a/BaseTools/Conf/tools_def.template b/BaseTools/Conf/tools_def.template
index 90f4105506e5..47d8c379d9f2 100755
--- a/BaseTools/Conf/tools_def.template
+++ b/BaseTools/Conf/tools_def.template
@@ -745,6 +745,7 @@ DEFINE GCC_LOONGARCH64_CC_FLAGS = DEF(GCC_ALL_CC_FLAGS) -mabi=lp64d -fno-asyn
DEFINE GCC_ARM_CC_XIPFLAGS = -mno-unaligned-access
DEFINE GCC_AARCH64_CC_FLAGS = DEF(GCC_ALL_CC_FLAGS) -mlittle-endian -fno-short-enums -fverbose-asm -funsigned-char -ffunction-sections -fdata-sections -Wno-address -fno-asynchronous-unwind-tables -fno-unwind-tables -fno-pic -fno-pie -ffixed-x18
DEFINE GCC_AARCH64_CC_XIPFLAGS = -mstrict-align -mgeneral-regs-only
+DEFINE GCC_RISCV64_CC_XIPFLAGS = -mstrict-align -mgeneral-regs-only
DEFINE GCC_DLINK_FLAGS_COMMON = -nostdlib --pie
DEFINE GCC_DLINK2_FLAGS_COMMON = -Wl,--script=$(EDK_TOOLS_PATH)/Scripts/GccBase.lds
DEFINE GCC_IA32_X64_DLINK_COMMON = DEF(GCC_DLINK_FLAGS_COMMON) --gc-sections
@@ -2023,6 +2024,57 @@ DEFINE CLANGDWARF_AARCH64_DLINK_FLAGS = DEF(CLANGDWARF_AARCH64_TARGET) DEF(GCC_
RELEASE_CLANGDWARF_AARCH64_CC_FLAGS = DEF(CLANGDWARF_AARCH64_CC_FLAGS) $(PLATFORM_FLAGS) -flto -O3
RELEASE_CLANGDWARF_AARCH64_DLINK_FLAGS = DEF(CLANGDWARF_AARCH64_DLINK_FLAGS) -flto -Wl,-O3 -fuse-ld=lld -L$(WORKSPACE)/ArmPkg/Library/GccLto -llto-aarch64 -Wl,-plugin-opt=-pass-through=-llto-aarch64 -Wl,--no-pie,--no-relax
+##################
+# CLANGDWARF RISCV64 definitions
+##################
+DEFINE CLANGDWARF_RISCV64_TARGET = -target riscv64-linux-gnu
+DEFINE CLANGDWARF_RISCV64_CC_FLAGS = DEF(GCC5_RISCV64_CC_FLAGS) DEF(CLANGDWARF_RISCV64_TARGET) DEF(CLANGDWARF_WARNING_OVERRIDES)
+
+# This is similar to GCC flags but without -n
+DEFINE CLANGDWARF_RISCV64_ALL_DLINK_COMMON = -nostdlib -Wl,-q,--gc-sections -z common-page-size=0x40
+DEFINE CLANGDWARF_RISCV64_ALL_DLINK_FLAGS = DEF(CLANGDWARF_RISCV64_ALL_DLINK_COMMON) -Wl,--entry,$(IMAGE_ENTRY_POINT) -u $(IMAGE_ENTRY_POINT) -Wl,-Map,$(DEST_DIR_DEBUG)/$(BASE_NAME).map
+DEFINE CLANGDWARF_RISCV64_DLINK_FLAGS = DEF(CLANGDWARF_RISCV64_TARGET) DEF(CLANGDWARF_RISCV64_ALL_DLINK_FLAGS) -Wl,-melf64lriscv,--oformat=elf64-littleriscv,--no-relax
+
+*_CLANGDWARF_RISCV64_PP_FLAGS = DEF(GCC_PP_FLAGS)
+*_CLANGDWARF_RISCV64_ASLCC_FLAGS = DEF(GCC_ASLCC_FLAGS)
+*_CLANGDWARF_RISCV64_APP_FLAGS =
+*_CLANGDWARF_RISCV64_ASL_FLAGS = DEF(IASL_FLAGS)
+*_CLANGDWARF_RISCV64_ASL_OUTFLAGS = DEF(IASL_OUTFLAGS)
+*_CLANGDWARF_RISCV64_DTCPP_FLAGS = DEF(GCC_DTCPP_FLAGS)
+*_CLANGDWARF_RISCV64_DEPS_FLAGS = DEF(GCC_DEPS_FLAGS)
+
+*_CLANGDWARF_RISCV64_CC_PATH = ENV(CLANGDWARF_BIN)clang
+*_CLANGDWARF_RISCV64_ASM_PATH = ENV(CLANGDWARF_BIN)clang
+*_CLANGDWARF_RISCV64_PP_PATH = ENV(CLANGDWARF_BIN)clang
+*_CLANGDWARF_RISCV64_VFRPP_PATH = ENV(CLANGDWARF_BIN)clang
+*_CLANGDWARF_RISCV64_ASLCC_PATH = ENV(CLANGDWARF_BIN)clang
+*_CLANGDWARF_RISCV64_ASLPP_PATH = ENV(CLANGDWARF_BIN)clang
+*_CLANGDWARF_RISCV64_DLINK_PATH = ENV(CLANGDWARF_BIN)clang
+*_CLANGDWARF_RISCV64_ASLDLINK_PATH = ENV(CLANGDWARF_BIN)clang
+
+*_CLANGDWARF_RISCV64_SLINK_PATH = ENV(CLANGDWARF_BIN)llvm-ar
+*_CLANGDWARF_RISCV64_RC_PATH = ENV(CLANGDWARF_BIN)llvm-objcopy
+
+*_CLANGDWARF_RISCV64_ASLCC_FLAGS = DEF(GCC_ASLCC_FLAGS) -flto
+*_CLANGDWARF_RISCV64_ASLDLINK_FLAGS = DEF(CLANGDWARF_RISCV64_TARGET) DEF(GCC5_RISCV32_RISCV64_ASLDLINK_FLAGS)
+*_CLANGDWARF_RISCV64_ASM_FLAGS = DEF(GCC_ASM_FLAGS) DEF(CLANGDWARF_RISCV64_TARGET) $(PLATFORM_FLAGS) -Qunused-arguments -mabi=lp64 -mno-relax -flto
+*_CLANGDWARF_RISCV64_DLINK_FLAGS = DEF(CLANGDWARF_RISCV64_TARGET) DEF(GCC5_RISCV64_DLINK_FLAGS)
+*_CLANGDWARF_RISCV64_DLINK_XIPFLAGS = -z common-page-size=0x20
+*_CLANGDWARF_RISCV64_DLINK2_FLAGS = DEF(GCC_DLINK2_FLAGS_COMMON) -Wl,--defsym=PECOFF_HEADER_SIZE=0x240
+*_CLANGDWARF_RISCV64_PLATFORM_FLAGS =
+*_CLANGDWARF_RISCV64_PP_FLAGS = DEF(GCC_PP_FLAGS) DEF(CLANGDWARF_RISCV64_TARGET) $(PLATFORM_FLAGS)
+*_CLANGDWARF_RISCV64_RC_FLAGS = DEF(GCC_RISCV64_RC_FLAGS)
+*_CLANGDWARF_RISCV64_VFRPP_FLAGS = DEF(GCC_VFRPP_FLAGS) DEF(CLANGDWARF_RISCV64_TARGET) $(PLATFORM_FLAGS)
+*_CLANGDWARF_RISCV64_ASLPP_FLAGS = DEF(GCC_ASLPP_FLAGS) DEF(CLANGDWARF_RISCV64_TARGET)
+*_CLANGDWARF_RISCV64_CC_XIPFLAGS = DEF(GCC_RISCV64_CC_XIPFLAGS)
+
+ DEBUG_CLANGDWARF_RISCV64_CC_FLAGS = DEF(CLANGDWARF_RISCV64_CC_FLAGS) $(PLATFORM_FLAGS) -flto -O1
+ DEBUG_CLANGDWARF_RISCV64_DLINK_FLAGS = DEF(CLANGDWARF_RISCV64_DLINK_FLAGS) -flto -Wl,-O1 -fuse-ld=lld -Wl,--no-pie,--no-relax
+ NOOPT_CLANGDWARF_RISCV64_CC_FLAGS = DEF(CLANGDWARF_RISCV64_CC_FLAGS) $(PLATFORM_FLAGS) -O0
+ NOOPT_CLANGDWARF_RISCV64_DLINK_FLAGS = DEF(CLANGDWARF_RISCV64_DLINK_FLAGS) -fuse-ld=lld -Wl,--no-pie,--no-relax
+RELEASE_CLANGDWARF_RISCV64_CC_FLAGS = DEF(CLANGDWARF_RISCV64_CC_FLAGS) $(PLATFORM_FLAGS) -flto -O3
+RELEASE_CLANGDWARF_RISCV64_DLINK_FLAGS = DEF(CLANGDWARF_RISCV64_DLINK_FLAGS) -flto -Wl,-O3 -fuse-ld=lld -Wl,--no-pie,--no-relax
+
#
#
# XCODE5 support
--
2.34.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* 回复: [PATCH 3/4] BaseTools/tools_def: Add CLANGDWARF support for RISC-V
2023-07-03 8:08 ` [PATCH 3/4] BaseTools/tools_def: Add CLANGDWARF support for RISC-V Sunil V L
@ 2023-07-10 1:52 ` gaoliming
2023-07-10 9:29 ` [edk2-devel] " Sunil V L
0 siblings, 1 reply; 8+ messages in thread
From: gaoliming @ 2023-07-10 1:52 UTC (permalink / raw)
To: 'Sunil V L', devel
Cc: 'Rebecca Cran', 'Bob Feng', 'Yuwei Chen',
'Ard Biesheuvel'
Sunil:
I add my comments below.
> -----邮件原件-----
> 发件人: Sunil V L <sunilvl@ventanamicro.com>
> 发送时间: 2023年7月3日 16:09
> 收件人: devel@edk2.groups.io
> 抄送: Sunil V L <sunilvl@ventanamicro.com>; Rebecca Cran
> <rebecca@bsdio.com>; Liming Gao <gaoliming@byosoft.com.cn>; Bob Feng
> <bob.c.feng@intel.com>; Yuwei Chen <yuwei.chen@intel.com>; Ard
> Biesheuvel <ardb+tianocore@kernel.org>
> 主题: [PATCH 3/4] BaseTools/tools_def: Add CLANGDWARF support for
> RISC-V
>
> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4478
>
> Add tools_def definitions to support CLANGDWARF toolchain
> for RISC-V. This uses clang and the llvm LLD linker. This
> helps people by not requiring to install multiple
> cross compilers for different architectures.
>
> Cc: Rebecca Cran <rebecca@bsdio.com>
> Cc: Liming Gao <gaoliming@byosoft.com.cn>
> Cc: Bob Feng <bob.c.feng@intel.com>
> Cc: Yuwei Chen <yuwei.chen@intel.com>
> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
>
> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
> ---
> BaseTools/Conf/tools_def.template | 52
> +++++++++++++++++++++++++++++++
> 1 file changed, 52 insertions(+)
>
> diff --git a/BaseTools/Conf/tools_def.template
> b/BaseTools/Conf/tools_def.template
> index 90f4105506e5..47d8c379d9f2 100755
> --- a/BaseTools/Conf/tools_def.template
> +++ b/BaseTools/Conf/tools_def.template
> @@ -745,6 +745,7 @@ DEFINE GCC_LOONGARCH64_CC_FLAGS =
> DEF(GCC_ALL_CC_FLAGS) -mabi=lp64d -fno-asyn
> DEFINE GCC_ARM_CC_XIPFLAGS = -mno-unaligned-access
> DEFINE GCC_AARCH64_CC_FLAGS = DEF(GCC_ALL_CC_FLAGS)
> -mlittle-endian -fno-short-enums -fverbose-asm -funsigned-char
> -ffunction-sections -fdata-sections -Wno-address
> -fno-asynchronous-unwind-tables -fno-unwind-tables -fno-pic -fno-pie
> -ffixed-x18
> DEFINE GCC_AARCH64_CC_XIPFLAGS = -mstrict-align
> -mgeneral-regs-only
> +DEFINE GCC_RISCV64_CC_XIPFLAGS = -mstrict-align
> -mgeneral-regs-only
> DEFINE GCC_DLINK_FLAGS_COMMON = -nostdlib --pie
> DEFINE GCC_DLINK2_FLAGS_COMMON =
> -Wl,--script=$(EDK_TOOLS_PATH)/Scripts/GccBase.lds
> DEFINE GCC_IA32_X64_DLINK_COMMON =
> DEF(GCC_DLINK_FLAGS_COMMON) --gc-sections
> @@ -2023,6 +2024,57 @@ DEFINE CLANGDWARF_AARCH64_DLINK_FLAGS
> = DEF(CLANGDWARF_AARCH64_TARGET) DEF(GCC_
> RELEASE_CLANGDWARF_AARCH64_CC_FLAGS =
> DEF(CLANGDWARF_AARCH64_CC_FLAGS) $(PLATFORM_FLAGS) -flto -O3
> RELEASE_CLANGDWARF_AARCH64_DLINK_FLAGS =
> DEF(CLANGDWARF_AARCH64_DLINK_FLAGS) -flto -Wl,-O3 -fuse-ld=lld
> -L$(WORKSPACE)/ArmPkg/Library/GccLto -llto-aarch64
> -Wl,-plugin-opt=-pass-through=-llto-aarch64 -Wl,--no-pie,--no-relax
>
> +##################
> +# CLANGDWARF RISCV64 definitions
> +##################
> +DEFINE CLANGDWARF_RISCV64_TARGET = -target riscv64-linux-gnu
> +DEFINE CLANGDWARF_RISCV64_CC_FLAGS =
> DEF(GCC5_RISCV64_CC_FLAGS) DEF(CLANGDWARF_RISCV64_TARGET)
> DEF(CLANGDWARF_WARNING_OVERRIDES)
> +
> +# This is similar to GCC flags but without -n
> +DEFINE CLANGDWARF_RISCV64_ALL_DLINK_COMMON = -nostdlib
> -Wl,-q,--gc-sections -z common-page-size=0x40
> +DEFINE CLANGDWARF_RISCV64_ALL_DLINK_FLAGS =
> DEF(CLANGDWARF_RISCV64_ALL_DLINK_COMMON)
> -Wl,--entry,$(IMAGE_ENTRY_POINT) -u $(IMAGE_ENTRY_POINT)
> -Wl,-Map,$(DEST_DIR_DEBUG)/$(BASE_NAME).map
> +DEFINE CLANGDWARF_RISCV64_DLINK_FLAGS =
> DEF(CLANGDWARF_RISCV64_TARGET)
> DEF(CLANGDWARF_RISCV64_ALL_DLINK_FLAGS)
> -Wl,-melf64lriscv,--oformat=elf64-littleriscv,--no-relax
> +
> +*_CLANGDWARF_RISCV64_PP_FLAGS = DEF(GCC_PP_FLAGS)
> +*_CLANGDWARF_RISCV64_ASLCC_FLAGS = DEF(GCC_ASLCC_FLAGS)
> +*_CLANGDWARF_RISCV64_APP_FLAGS =
> +*_CLANGDWARF_RISCV64_ASL_FLAGS = DEF(IASL_FLAGS)
> +*_CLANGDWARF_RISCV64_ASL_OUTFLAGS = DEF(IASL_OUTFLAGS)
> +*_CLANGDWARF_RISCV64_DTCPP_FLAGS = DEF(GCC_DTCPP_FLAGS)
> +*_CLANGDWARF_RISCV64_DEPS_FLAGS = DEF(GCC_DEPS_FLAGS)
> +
> +*_CLANGDWARF_RISCV64_CC_PATH =
> ENV(CLANGDWARF_BIN)clang
> +*_CLANGDWARF_RISCV64_ASM_PATH =
> ENV(CLANGDWARF_BIN)clang
> +*_CLANGDWARF_RISCV64_PP_PATH =
> ENV(CLANGDWARF_BIN)clang
> +*_CLANGDWARF_RISCV64_VFRPP_PATH =
> ENV(CLANGDWARF_BIN)clang
> +*_CLANGDWARF_RISCV64_ASLCC_PATH =
> ENV(CLANGDWARF_BIN)clang
> +*_CLANGDWARF_RISCV64_ASLPP_PATH =
> ENV(CLANGDWARF_BIN)clang
> +*_CLANGDWARF_RISCV64_DLINK_PATH =
> ENV(CLANGDWARF_BIN)clang
> +*_CLANGDWARF_RISCV64_ASLDLINK_PATH =
> ENV(CLANGDWARF_BIN)clang
> +
> +*_CLANGDWARF_RISCV64_SLINK_PATH =
> ENV(CLANGDWARF_BIN)llvm-ar
> +*_CLANGDWARF_RISCV64_RC_PATH =
> ENV(CLANGDWARF_BIN)llvm-objcopy
> +
> +*_CLANGDWARF_RISCV64_ASLCC_FLAGS = DEF(GCC_ASLCC_FLAGS)
> -flto
Here should be -fno-lto. This option should be same for the different ARCHs.
> +*_CLANGDWARF_RISCV64_ASLDLINK_FLAGS =
> DEF(CLANGDWARF_RISCV64_TARGET)
> DEF(GCC5_RISCV32_RISCV64_ASLDLINK_FLAGS)
> +*_CLANGDWARF_RISCV64_ASM_FLAGS = DEF(GCC_ASM_FLAGS)
> DEF(CLANGDWARF_RISCV64_TARGET) $(PLATFORM_FLAGS)
> -Qunused-arguments -mabi=lp64 -mno-relax -flto
Here should be no -flto. Please confirm.
Thanks
Liming
> +*_CLANGDWARF_RISCV64_DLINK_FLAGS =
> DEF(CLANGDWARF_RISCV64_TARGET) DEF(GCC5_RISCV64_DLINK_FLAGS)
> +*_CLANGDWARF_RISCV64_DLINK_XIPFLAGS = -z common-page-size=0x20
> +*_CLANGDWARF_RISCV64_DLINK2_FLAGS =
> DEF(GCC_DLINK2_FLAGS_COMMON)
> -Wl,--defsym=PECOFF_HEADER_SIZE=0x240
> +*_CLANGDWARF_RISCV64_PLATFORM_FLAGS =
> +*_CLANGDWARF_RISCV64_PP_FLAGS = DEF(GCC_PP_FLAGS)
> DEF(CLANGDWARF_RISCV64_TARGET) $(PLATFORM_FLAGS)
> +*_CLANGDWARF_RISCV64_RC_FLAGS =
> DEF(GCC_RISCV64_RC_FLAGS)
> +*_CLANGDWARF_RISCV64_VFRPP_FLAGS = DEF(GCC_VFRPP_FLAGS)
> DEF(CLANGDWARF_RISCV64_TARGET) $(PLATFORM_FLAGS)
> +*_CLANGDWARF_RISCV64_ASLPP_FLAGS = DEF(GCC_ASLPP_FLAGS)
> DEF(CLANGDWARF_RISCV64_TARGET)
> +*_CLANGDWARF_RISCV64_CC_XIPFLAGS =
> DEF(GCC_RISCV64_CC_XIPFLAGS)
> +
> + DEBUG_CLANGDWARF_RISCV64_CC_FLAGS =
> DEF(CLANGDWARF_RISCV64_CC_FLAGS) $(PLATFORM_FLAGS) -flto -O1
> + DEBUG_CLANGDWARF_RISCV64_DLINK_FLAGS =
> DEF(CLANGDWARF_RISCV64_DLINK_FLAGS) -flto -Wl,-O1 -fuse-ld=lld
> -Wl,--no-pie,--no-relax
> + NOOPT_CLANGDWARF_RISCV64_CC_FLAGS =
> DEF(CLANGDWARF_RISCV64_CC_FLAGS) $(PLATFORM_FLAGS) -O0
> + NOOPT_CLANGDWARF_RISCV64_DLINK_FLAGS =
> DEF(CLANGDWARF_RISCV64_DLINK_FLAGS) -fuse-ld=lld
> -Wl,--no-pie,--no-relax
> +RELEASE_CLANGDWARF_RISCV64_CC_FLAGS =
> DEF(CLANGDWARF_RISCV64_CC_FLAGS) $(PLATFORM_FLAGS) -flto -O3
> +RELEASE_CLANGDWARF_RISCV64_DLINK_FLAGS =
> DEF(CLANGDWARF_RISCV64_DLINK_FLAGS) -flto -Wl,-O3 -fuse-ld=lld
> -Wl,--no-pie,--no-relax
> +
> #
> #
> # XCODE5 support
> --
> 2.34.1
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [edk2-devel] 回复: [PATCH 3/4] BaseTools/tools_def: Add CLANGDWARF support for RISC-V
2023-07-10 1:52 ` 回复: " gaoliming
@ 2023-07-10 9:29 ` Sunil V L
0 siblings, 0 replies; 8+ messages in thread
From: Sunil V L @ 2023-07-10 9:29 UTC (permalink / raw)
To: devel, gaoliming
Cc: 'Rebecca Cran', 'Bob Feng', 'Yuwei Chen',
'Ard Biesheuvel'
Hi Liming,
On Mon, Jul 10, 2023 at 09:52:18AM +0800, gaoliming via groups.io wrote:
> Sunil:
> I add my comments below.
>
> > -----邮件原件-----
> > 发件人: Sunil V L <sunilvl@ventanamicro.com>
> > 发送时间: 2023年7月3日 16:09
> > 收件人: devel@edk2.groups.io
> > 抄送: Sunil V L <sunilvl@ventanamicro.com>; Rebecca Cran
> > <rebecca@bsdio.com>; Liming Gao <gaoliming@byosoft.com.cn>; Bob Feng
> > <bob.c.feng@intel.com>; Yuwei Chen <yuwei.chen@intel.com>; Ard
> > Biesheuvel <ardb+tianocore@kernel.org>
> > 主题: [PATCH 3/4] BaseTools/tools_def: Add CLANGDWARF support for
> > RISC-V
> >
> > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4478
> >
> > Add tools_def definitions to support CLANGDWARF toolchain
> > for RISC-V. This uses clang and the llvm LLD linker. This
> > helps people by not requiring to install multiple
> > cross compilers for different architectures.
> >
> > Cc: Rebecca Cran <rebecca@bsdio.com>
> > Cc: Liming Gao <gaoliming@byosoft.com.cn>
> > Cc: Bob Feng <bob.c.feng@intel.com>
> > Cc: Yuwei Chen <yuwei.chen@intel.com>
> > Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
> >
> > Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
> > ---
> > BaseTools/Conf/tools_def.template | 52
> > +++++++++++++++++++++++++++++++
> > 1 file changed, 52 insertions(+)
> >
> > diff --git a/BaseTools/Conf/tools_def.template
> > b/BaseTools/Conf/tools_def.template
> > index 90f4105506e5..47d8c379d9f2 100755
> > --- a/BaseTools/Conf/tools_def.template
> > +++ b/BaseTools/Conf/tools_def.template
> > @@ -745,6 +745,7 @@ DEFINE GCC_LOONGARCH64_CC_FLAGS =
> > DEF(GCC_ALL_CC_FLAGS) -mabi=lp64d -fno-asyn
> > DEFINE GCC_ARM_CC_XIPFLAGS = -mno-unaligned-access
> > DEFINE GCC_AARCH64_CC_FLAGS = DEF(GCC_ALL_CC_FLAGS)
> > -mlittle-endian -fno-short-enums -fverbose-asm -funsigned-char
> > -ffunction-sections -fdata-sections -Wno-address
> > -fno-asynchronous-unwind-tables -fno-unwind-tables -fno-pic -fno-pie
> > -ffixed-x18
> > DEFINE GCC_AARCH64_CC_XIPFLAGS = -mstrict-align
> > -mgeneral-regs-only
> > +DEFINE GCC_RISCV64_CC_XIPFLAGS = -mstrict-align
> > -mgeneral-regs-only
> > DEFINE GCC_DLINK_FLAGS_COMMON = -nostdlib --pie
> > DEFINE GCC_DLINK2_FLAGS_COMMON =
> > -Wl,--script=$(EDK_TOOLS_PATH)/Scripts/GccBase.lds
> > DEFINE GCC_IA32_X64_DLINK_COMMON =
> > DEF(GCC_DLINK_FLAGS_COMMON) --gc-sections
> > @@ -2023,6 +2024,57 @@ DEFINE CLANGDWARF_AARCH64_DLINK_FLAGS
> > = DEF(CLANGDWARF_AARCH64_TARGET) DEF(GCC_
> > RELEASE_CLANGDWARF_AARCH64_CC_FLAGS =
> > DEF(CLANGDWARF_AARCH64_CC_FLAGS) $(PLATFORM_FLAGS) -flto -O3
> > RELEASE_CLANGDWARF_AARCH64_DLINK_FLAGS =
> > DEF(CLANGDWARF_AARCH64_DLINK_FLAGS) -flto -Wl,-O3 -fuse-ld=lld
> > -L$(WORKSPACE)/ArmPkg/Library/GccLto -llto-aarch64
> > -Wl,-plugin-opt=-pass-through=-llto-aarch64 -Wl,--no-pie,--no-relax
> >
> > +##################
> > +# CLANGDWARF RISCV64 definitions
> > +##################
> > +DEFINE CLANGDWARF_RISCV64_TARGET = -target riscv64-linux-gnu
> > +DEFINE CLANGDWARF_RISCV64_CC_FLAGS =
> > DEF(GCC5_RISCV64_CC_FLAGS) DEF(CLANGDWARF_RISCV64_TARGET)
> > DEF(CLANGDWARF_WARNING_OVERRIDES)
> > +
> > +# This is similar to GCC flags but without -n
> > +DEFINE CLANGDWARF_RISCV64_ALL_DLINK_COMMON = -nostdlib
> > -Wl,-q,--gc-sections -z common-page-size=0x40
> > +DEFINE CLANGDWARF_RISCV64_ALL_DLINK_FLAGS =
> > DEF(CLANGDWARF_RISCV64_ALL_DLINK_COMMON)
> > -Wl,--entry,$(IMAGE_ENTRY_POINT) -u $(IMAGE_ENTRY_POINT)
> > -Wl,-Map,$(DEST_DIR_DEBUG)/$(BASE_NAME).map
> > +DEFINE CLANGDWARF_RISCV64_DLINK_FLAGS =
> > DEF(CLANGDWARF_RISCV64_TARGET)
> > DEF(CLANGDWARF_RISCV64_ALL_DLINK_FLAGS)
> > -Wl,-melf64lriscv,--oformat=elf64-littleriscv,--no-relax
> > +
> > +*_CLANGDWARF_RISCV64_PP_FLAGS = DEF(GCC_PP_FLAGS)
> > +*_CLANGDWARF_RISCV64_ASLCC_FLAGS = DEF(GCC_ASLCC_FLAGS)
> > +*_CLANGDWARF_RISCV64_APP_FLAGS =
> > +*_CLANGDWARF_RISCV64_ASL_FLAGS = DEF(IASL_FLAGS)
> > +*_CLANGDWARF_RISCV64_ASL_OUTFLAGS = DEF(IASL_OUTFLAGS)
> > +*_CLANGDWARF_RISCV64_DTCPP_FLAGS = DEF(GCC_DTCPP_FLAGS)
> > +*_CLANGDWARF_RISCV64_DEPS_FLAGS = DEF(GCC_DEPS_FLAGS)
> > +
> > +*_CLANGDWARF_RISCV64_CC_PATH =
> > ENV(CLANGDWARF_BIN)clang
> > +*_CLANGDWARF_RISCV64_ASM_PATH =
> > ENV(CLANGDWARF_BIN)clang
> > +*_CLANGDWARF_RISCV64_PP_PATH =
> > ENV(CLANGDWARF_BIN)clang
> > +*_CLANGDWARF_RISCV64_VFRPP_PATH =
> > ENV(CLANGDWARF_BIN)clang
> > +*_CLANGDWARF_RISCV64_ASLCC_PATH =
> > ENV(CLANGDWARF_BIN)clang
> > +*_CLANGDWARF_RISCV64_ASLPP_PATH =
> > ENV(CLANGDWARF_BIN)clang
> > +*_CLANGDWARF_RISCV64_DLINK_PATH =
> > ENV(CLANGDWARF_BIN)clang
> > +*_CLANGDWARF_RISCV64_ASLDLINK_PATH =
> > ENV(CLANGDWARF_BIN)clang
> > +
> > +*_CLANGDWARF_RISCV64_SLINK_PATH =
> > ENV(CLANGDWARF_BIN)llvm-ar
> > +*_CLANGDWARF_RISCV64_RC_PATH =
> > ENV(CLANGDWARF_BIN)llvm-objcopy
> > +
> > +*_CLANGDWARF_RISCV64_ASLCC_FLAGS = DEF(GCC_ASLCC_FLAGS)
> > -flto
> Here should be -fno-lto. This option should be same for the different ARCHs.
>
>
> > +*_CLANGDWARF_RISCV64_ASLDLINK_FLAGS =
> > DEF(CLANGDWARF_RISCV64_TARGET)
> > DEF(GCC5_RISCV32_RISCV64_ASLDLINK_FLAGS)
> > +*_CLANGDWARF_RISCV64_ASM_FLAGS = DEF(GCC_ASM_FLAGS)
> > DEF(CLANGDWARF_RISCV64_TARGET) $(PLATFORM_FLAGS)
> > -Qunused-arguments -mabi=lp64 -mno-relax -flto
>
> Here should be no -flto. Please confirm.
>
Good catch!. I agree. Let me fix these issues and send next version.
Thanks!
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 4/4] OvmfPkg/RiscVVirt: Update README for CLANGDWARF support
2023-07-03 8:08 [PATCH 0/4] OvmfPkg/RiscVVirt: Add CLANGDWARF toolchain support Sunil V L
` (2 preceding siblings ...)
2023-07-03 8:08 ` [PATCH 3/4] BaseTools/tools_def: Add CLANGDWARF support for RISC-V Sunil V L
@ 2023-07-03 8:08 ` Sunil V L
2023-07-03 12:15 ` [PATCH 0/4] OvmfPkg/RiscVVirt: Add CLANGDWARF toolchain support Ard Biesheuvel
4 siblings, 0 replies; 8+ messages in thread
From: Sunil V L @ 2023-07-03 8:08 UTC (permalink / raw)
To: devel
Cc: Sunil V L, Ard Biesheuvel, Jiewen Yao, Jordan Justen,
Gerd Hoffmann, Andrei Warkentin, Heinrich Schuchardt
Update the README with instruction to build using CLANGDWARF
toolchain.
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Andrei Warkentin <andrei.warkentin@intel.com>
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
---
OvmfPkg/RiscVVirt/README.md | 28 +++++++++++++++++++++++++---
1 file changed, 25 insertions(+), 3 deletions(-)
diff --git a/OvmfPkg/RiscVVirt/README.md b/OvmfPkg/RiscVVirt/README.md
index 950694419e8b..8c3ac37b802a 100644
--- a/OvmfPkg/RiscVVirt/README.md
+++ b/OvmfPkg/RiscVVirt/README.md
@@ -12,24 +12,46 @@ The minimum QEMU version required is
[7efd65423a](https://github.com/qemu/qemu/commit/7efd65423ab22e6f5890ca08ae40c84d6660242f)
which supports separate pflash devices for EDK2 code and variable storage.
+## Get edk2 sources
+
+ git clone --recurse-submodule git@github.com:tianocore/edk2.git
+
## Build
+
+### Using GCC toolchain
+**Prerequisite**: RISC-V GNU compiler toolchain should be installed.
+
export WORKSPACE=`pwd`
export GCC5_RISCV64_PREFIX=riscv64-linux-gnu-
export PACKAGES_PATH=$WORKSPACE/edk2
export EDK_TOOLS_PATH=$WORKSPACE/edk2/BaseTools
- source edk2/edksetup.sh
+ source edk2/edksetup.sh --reconfig
make -C edk2/BaseTools
source edk2/edksetup.sh BaseTools
build -a RISCV64 --buildtarget RELEASE -p OvmfPkg/RiscVVirt/RiscVVirtQemu.dsc -t GCC5
+### Using CLANGDWARF toolchain (clang + lld)
+**Prerequisite**: LLVM toolchain with clang and lld should be installed.
+
+ export WORKSPACE=`pwd`
+ export CLANGDWARF_BIN=/usr/bin/
+ export PACKAGES_PATH=$WORKSPACE/edk2
+ export EDK_TOOLS_PATH=$WORKSPACE/edk2/BaseTools
+ source edk2/edksetup.sh --reconfig
+ make -C edk2/BaseTools
+ source edk2/edksetup.sh BaseTools
+ build -a RISCV64 --buildtarget RELEASE -p OvmfPkg/RiscVVirt/RiscVVirtQemu.dsc -t CLANGDWARF
+
+After a successful build, two files namely **RISCV_VIRT_CODE.fd** and **RISCV_VIRT_VARS.fd** are created.
+
## Test
Below example shows how to boot openSUSE Tumbleweed E20.
1) RISC-V QEMU pflash devices should be of of size 32MiB.
- `truncate -s 32M Build/RiscVVirtQemu/RELEASE_GCC5/FV/RISCV_VIRT_CODE.fd`
+ `truncate -s 32M RISCV_VIRT_CODE.fd`
- `truncate -s 32M Build/RiscVVirtQemu/RELEASE_GCC5/FV/RISCV_VIRT_VARS.fd`
+ `truncate -s 32M RISCV_VIRT_VARS.fd`
2) Running QEMU
--
2.34.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH 0/4] OvmfPkg/RiscVVirt: Add CLANGDWARF toolchain support
2023-07-03 8:08 [PATCH 0/4] OvmfPkg/RiscVVirt: Add CLANGDWARF toolchain support Sunil V L
` (3 preceding siblings ...)
2023-07-03 8:08 ` [PATCH 4/4] OvmfPkg/RiscVVirt: Update README for CLANGDWARF support Sunil V L
@ 2023-07-03 12:15 ` Ard Biesheuvel
4 siblings, 0 replies; 8+ messages in thread
From: Ard Biesheuvel @ 2023-07-03 12:15 UTC (permalink / raw)
To: Sunil V L
Cc: devel, Rebecca Cran, Liming Gao, Bob Feng, Yuwei Chen,
Ard Biesheuvel, Jiewen Yao, Jordan Justen, Andrei Warkentin,
Heinrich Schuchardt
On Mon, 3 Jul 2023 at 10:08, Sunil V L <sunilvl@ventanamicro.com> wrote:
>
> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4478
>
> This series adds support for building RiscVVirtQemu EDK2 using
> CLANGDWARF toolchain. Adding this support helps people to use
> the same toolchain to build EDK2 for different architectures.
>
> Cc: Rebecca Cran <rebecca@bsdio.com>
> Cc: Liming Gao <gaoliming@byosoft.com.cn>
> Cc: Bob Feng <bob.c.feng@intel.com>
> Cc: Yuwei Chen <yuwei.chen@intel.com>
> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
> Cc: Jiewen Yao <jiewen.yao@intel.com>
> Cc: Jordan Justen <jordan.l.justen@intel.com>
> Cc Gerd Hoffmann <kraxel@redhat.com>
> Cc: Andrei Warkentin <andrei.warkentin@intel.com>
> Cc: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
>
> Sunil V L (4):
> OvmfPkg/RiscVVirt: use 'auto' alignment and FIXED for XIP modules
> OvmfPkg/RiscVVirt: SecEntry: Remove unnecessary assembly directives
> BaseTools/tools_def: Add CLANGDWARF support for RISC-V
> OvmfPkg/RiscVVirt: Update README for CLANGDWARF support
>
This looks good to me, although I am not an expert when it comes to
RISC-V specifics
Acked-by: Ard Biesheuvel <ardb@kernel.org>
Thanks a lot for this work - it will surely make my life a bit easier
^ permalink raw reply [flat|nested] 8+ messages in thread