From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pl1-f170.google.com (mail-pl1-f170.google.com [209.85.214.170]) by mx.groups.io with SMTP id smtpd.web10.2972.1689090235007240389 for ; Tue, 11 Jul 2023 08:43:55 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="signature has expired" header.i=@ventanamicro.com header.s=google header.b=Tyjadj6z; spf=pass (domain: ventanamicro.com, ip: 209.85.214.170, mailfrom: sunilvl@ventanamicro.com) Received: by mail-pl1-f170.google.com with SMTP id d9443c01a7336-1b89600a37fso29670605ad.2 for ; Tue, 11 Jul 2023 08:43:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1689090234; x=1691682234; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UqYp51pcdjezY1YrLXHIcvbXbHLh23QPdUvKWb5jkB8=; b=Tyjadj6zA299rBOLYH0s2WsvApaNlT0wGj3KHkOVgI5De2ykMc7swHqZEuqAx6+T1i wpJigkJD4kZO1KE27O3189cBvdEZGqp5VDE8tRsoFWuI7vITG7kItvSif16eh53BcYlU xhlOo0pp8OBGBLaoM0s9ZewokdqCzvShZpoUUuk30yPqOhzh00xY5pJ3VSqOBuP3C+AO eEmOQSyNWskmVa/vcEgvzxiDeOf5224mOJAmV5yAg782JFGPsBvvNxnhbzExQoNgcex4 2fykr5ijyZUVNuNqPrZOPiNGo2/SLlBRPhwfeuB2pqWqhklN2D81QpJBJkHBIGXU8kY5 egEg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689090234; x=1691682234; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UqYp51pcdjezY1YrLXHIcvbXbHLh23QPdUvKWb5jkB8=; b=EM58dT85fI0btEwG0nM/3slcT0l5yqBqrEnCn0n2CJGxPy79sEi8QeiHOjRwn2fu/G RgBHjlp1LPgx+6jVJBD5agLz/9cyeZ5gm5b5G60vVWJkeWZWex6tGfcSIFazT6NtAGoQ q/VtSZFkjk2rp49Qa4RDqVrGRjju0psXNo29PX72PBrgRL1N0Z3PR1Sz5892Q+JLZEWb 1wVNxMRZSuMQGteWeqd/I5gZ6GutvLj30qI02k9iHULIfFmrZR6sy1pTzrSRQNHIRgZ9 1N+nf0H0Jwb409QLklseNAB2sWRg3If8XHSabTLce+dOes6983166y8ae6IJWrIfpxu4 odtA== X-Gm-Message-State: ABy/qLaOuUvlA2+CBacAMlAPc5gGItW6ucg4rHLnzy48BpjFxAzkTaKE XkiLgkmYwbsS8cXLoUtT/H3ywA5hI6K0BAGzZX0= X-Google-Smtp-Source: APBJJlESCwfHR0qA56Gd9zR9TB2S4vZOwpstKYhSvXQSDw1Yjwe1mTDM9Z1RrUXFDDVbmjR/peCqGg== X-Received: by 2002:a17:903:441:b0:1b8:b26f:a6ac with SMTP id iw1-20020a170903044100b001b8b26fa6acmr13289707plb.5.1689090234285; Tue, 11 Jul 2023 08:43:54 -0700 (PDT) Return-Path: Received: from sunil-laptop.. ([106.51.184.72]) by smtp.gmail.com with ESMTPSA id k9-20020a170902694900b001b9f75c8c4dsm923084plt.52.2023.07.11.08.43.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jul 2023 08:43:54 -0700 (PDT) From: "Sunil V L" To: devel@edk2.groups.io Cc: Sunil V L , Rebecca Cran , Liming Gao , Bob Feng , Yuwei Chen , Ard Biesheuvel , Ard Biesheuvel Subject: [PATCH v2 3/4] BaseTools/tools_def: Add CLANGDWARF support for RISC-V Date: Tue, 11 Jul 2023 21:13:34 +0530 Message-Id: <20230711154335.586343-4-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230711154335.586343-1-sunilvl@ventanamicro.com> References: <20230711154335.586343-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4478 Add tools_def definitions to support CLANGDWARF toolchain for RISC-V. This uses clang and the llvm LLD linker. This helps people by not requiring to install multiple cross compilers for different architectures. Cc: Rebecca Cran Cc: Liming Gao Cc: Bob Feng Cc: Yuwei Chen Cc: Ard Biesheuvel Signed-off-by: Sunil V L Acked-by: Ard Biesheuvel --- BaseTools/Conf/tools_def.template | 53 +++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/BaseTools/Conf/tools_def.template b/BaseTools/Conf/tools_def.template index 90f4105506e5..1bf62362b611 100755 --- a/BaseTools/Conf/tools_def.template +++ b/BaseTools/Conf/tools_def.template @@ -745,6 +745,7 @@ DEFINE GCC_LOONGARCH64_CC_FLAGS = DEF(GCC_ALL_CC_FLAGS) -mabi=lp64d -fno-asyn DEFINE GCC_ARM_CC_XIPFLAGS = -mno-unaligned-access DEFINE GCC_AARCH64_CC_FLAGS = DEF(GCC_ALL_CC_FLAGS) -mlittle-endian -fno-short-enums -fverbose-asm -funsigned-char -ffunction-sections -fdata-sections -Wno-address -fno-asynchronous-unwind-tables -fno-unwind-tables -fno-pic -fno-pie -ffixed-x18 DEFINE GCC_AARCH64_CC_XIPFLAGS = -mstrict-align -mgeneral-regs-only +DEFINE GCC_RISCV64_CC_XIPFLAGS = -mstrict-align -mgeneral-regs-only DEFINE GCC_DLINK_FLAGS_COMMON = -nostdlib --pie DEFINE GCC_DLINK2_FLAGS_COMMON = -Wl,--script=$(EDK_TOOLS_PATH)/Scripts/GccBase.lds DEFINE GCC_IA32_X64_DLINK_COMMON = DEF(GCC_DLINK_FLAGS_COMMON) --gc-sections @@ -2023,6 +2024,58 @@ DEFINE CLANGDWARF_AARCH64_DLINK_FLAGS = DEF(CLANGDWARF_AARCH64_TARGET) DEF(GCC_ RELEASE_CLANGDWARF_AARCH64_CC_FLAGS = DEF(CLANGDWARF_AARCH64_CC_FLAGS) $(PLATFORM_FLAGS) -flto -O3 RELEASE_CLANGDWARF_AARCH64_DLINK_FLAGS = DEF(CLANGDWARF_AARCH64_DLINK_FLAGS) -flto -Wl,-O3 -fuse-ld=lld -L$(WORKSPACE)/ArmPkg/Library/GccLto -llto-aarch64 -Wl,-plugin-opt=-pass-through=-llto-aarch64 -Wl,--no-pie,--no-relax +################## +# CLANGDWARF RISCV64 definitions +################## +DEFINE CLANGDWARF_RISCV64_TARGET = -target riscv64-linux-gnu +DEFINE CLANGDWARF_RISCV64_CC_COMMON = DEF(GCC5_RISCV_ALL_CC_FLAGS) DEF(GCC5_RISCV_ALL_CC_FLAGS_WARNING_DISABLE) DEF(GCC5_RISCV_OPENSBI_TYPES) -march=DEF(GCC5_RISCV64_ARCH) -fno-builtin -fno-builtin-memcpy -fno-stack-protector -Wno-address -fno-asynchronous-unwind-tables -fno-unwind-tables -Wno-unused-but-set-variable -fpack-struct=8 -mcmodel=medany -mabi=lp64 -mno-relax +DEFINE CLANGDWARF_RISCV64_CC_FLAGS = DEF(CLANGDWARF_RISCV64_CC_COMMON) DEF(CLANGDWARF_RISCV64_TARGET) DEF(CLANGDWARF_WARNING_OVERRIDES) + +# This is similar to GCC flags but without -n +DEFINE CLANGDWARF_RISCV64_ALL_DLINK_COMMON = -nostdlib -Wl,-q,--gc-sections -z common-page-size=0x40 +DEFINE CLANGDWARF_RISCV64_ALL_DLINK_FLAGS = DEF(CLANGDWARF_RISCV64_ALL_DLINK_COMMON) -Wl,--entry,$(IMAGE_ENTRY_POINT) -u $(IMAGE_ENTRY_POINT) -Wl,-Map,$(DEST_DIR_DEBUG)/$(BASE_NAME).map +DEFINE CLANGDWARF_RISCV64_DLINK_FLAGS = DEF(CLANGDWARF_RISCV64_TARGET) DEF(CLANGDWARF_RISCV64_ALL_DLINK_FLAGS) -Wl,-melf64lriscv,--oformat=elf64-littleriscv,--no-relax + +*_CLANGDWARF_RISCV64_PP_FLAGS = DEF(GCC_PP_FLAGS) +*_CLANGDWARF_RISCV64_ASLCC_FLAGS = DEF(GCC_ASLCC_FLAGS) +*_CLANGDWARF_RISCV64_APP_FLAGS = +*_CLANGDWARF_RISCV64_ASL_FLAGS = DEF(IASL_FLAGS) +*_CLANGDWARF_RISCV64_ASL_OUTFLAGS = DEF(IASL_OUTFLAGS) +*_CLANGDWARF_RISCV64_DTCPP_FLAGS = DEF(GCC_DTCPP_FLAGS) +*_CLANGDWARF_RISCV64_DEPS_FLAGS = DEF(GCC_DEPS_FLAGS) + +*_CLANGDWARF_RISCV64_CC_PATH = ENV(CLANGDWARF_BIN)clang +*_CLANGDWARF_RISCV64_ASM_PATH = ENV(CLANGDWARF_BIN)clang +*_CLANGDWARF_RISCV64_PP_PATH = ENV(CLANGDWARF_BIN)clang +*_CLANGDWARF_RISCV64_VFRPP_PATH = ENV(CLANGDWARF_BIN)clang +*_CLANGDWARF_RISCV64_ASLCC_PATH = ENV(CLANGDWARF_BIN)clang +*_CLANGDWARF_RISCV64_ASLPP_PATH = ENV(CLANGDWARF_BIN)clang +*_CLANGDWARF_RISCV64_DLINK_PATH = ENV(CLANGDWARF_BIN)clang +*_CLANGDWARF_RISCV64_ASLDLINK_PATH = ENV(CLANGDWARF_BIN)clang + +*_CLANGDWARF_RISCV64_SLINK_PATH = ENV(CLANGDWARF_BIN)llvm-ar +*_CLANGDWARF_RISCV64_RC_PATH = ENV(CLANGDWARF_BIN)llvm-objcopy + +*_CLANGDWARF_RISCV64_ASLCC_FLAGS = DEF(GCC_ASLCC_FLAGS) -fno-lto +*_CLANGDWARF_RISCV64_ASLDLINK_FLAGS = DEF(CLANGDWARF_RISCV64_TARGET) DEF(GCC5_RISCV32_RISCV64_ASLDLINK_FLAGS) +*_CLANGDWARF_RISCV64_ASM_FLAGS = DEF(GCC_ASM_FLAGS) DEF(CLANGDWARF_RISCV64_TARGET) $(PLATFORM_FLAGS) -Qunused-arguments -mabi=lp64 -mno-relax +*_CLANGDWARF_RISCV64_DLINK_FLAGS = DEF(CLANGDWARF_RISCV64_TARGET) DEF(GCC5_RISCV64_DLINK_FLAGS) +*_CLANGDWARF_RISCV64_DLINK_XIPFLAGS = -z common-page-size=0x20 +*_CLANGDWARF_RISCV64_DLINK2_FLAGS = DEF(GCC_DLINK2_FLAGS_COMMON) -Wl,--defsym=PECOFF_HEADER_SIZE=0x240 +*_CLANGDWARF_RISCV64_PLATFORM_FLAGS = +*_CLANGDWARF_RISCV64_PP_FLAGS = DEF(GCC_PP_FLAGS) DEF(CLANGDWARF_RISCV64_TARGET) $(PLATFORM_FLAGS) +*_CLANGDWARF_RISCV64_RC_FLAGS = DEF(GCC_RISCV64_RC_FLAGS) +*_CLANGDWARF_RISCV64_VFRPP_FLAGS = DEF(GCC_VFRPP_FLAGS) DEF(CLANGDWARF_RISCV64_TARGET) $(PLATFORM_FLAGS) +*_CLANGDWARF_RISCV64_ASLPP_FLAGS = DEF(GCC_ASLPP_FLAGS) DEF(CLANGDWARF_RISCV64_TARGET) +*_CLANGDWARF_RISCV64_CC_XIPFLAGS = DEF(GCC_RISCV64_CC_XIPFLAGS) + + DEBUG_CLANGDWARF_RISCV64_CC_FLAGS = DEF(CLANGDWARF_RISCV64_CC_FLAGS) $(PLATFORM_FLAGS) -flto -O1 + DEBUG_CLANGDWARF_RISCV64_DLINK_FLAGS = DEF(CLANGDWARF_RISCV64_DLINK_FLAGS) -flto -Wl,-O1 -fuse-ld=lld -Wl,--no-pie,--no-relax + NOOPT_CLANGDWARF_RISCV64_CC_FLAGS = DEF(CLANGDWARF_RISCV64_CC_FLAGS) $(PLATFORM_FLAGS) -O0 + NOOPT_CLANGDWARF_RISCV64_DLINK_FLAGS = DEF(CLANGDWARF_RISCV64_DLINK_FLAGS) -fuse-ld=lld -Wl,--no-pie,--no-relax +RELEASE_CLANGDWARF_RISCV64_CC_FLAGS = DEF(CLANGDWARF_RISCV64_CC_FLAGS) $(PLATFORM_FLAGS) -flto -O3 +RELEASE_CLANGDWARF_RISCV64_DLINK_FLAGS = DEF(CLANGDWARF_RISCV64_DLINK_FLAGS) -flto -Wl,-O3 -fuse-ld=lld -Wl,--no-pie,--no-relax + # # # XCODE5 support -- 2.34.1