From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pl1-f174.google.com (mail-pl1-f174.google.com [209.85.214.174]) by mx.groups.io with SMTP id smtpd.web10.4364.1689240816710178900 for ; Thu, 13 Jul 2023 02:33:36 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@rivosinc-com.20221208.gappssmtp.com header.s=20221208 header.b=JteMvLwT; spf=pass (domain: rivosinc.com, ip: 209.85.214.174, mailfrom: dhaval@rivosinc.com) Received: by mail-pl1-f174.google.com with SMTP id d9443c01a7336-1b89b75dc1cso11919815ad.1 for ; Thu, 13 Jul 2023 02:33:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20221208.gappssmtp.com; s=20221208; t=1689240816; x=1691832816; h=content-transfer-encoding:mime-version:message-id:date:subject:to :from:from:to:cc:subject:date:message-id:reply-to; bh=eqBl1zaWXmxGcAj53F4bE/yShI8TPZxujTgVO2UdhB4=; b=JteMvLwTJNSHrdQCGaZmHJ+dBXsn5e661IMvUt4m8+vTIHfkRhjqqduG13h6Ge76M7 6pz1dxsM0Klnz9K3eTGVUDgDcARq/ilBLAyrxoVAH3Z4eWmEqY50opv2lIIClDDsI48b w41XUVBEZvkU/6wM7JMZ5IhqIyVBmV28ewA1gfmXmIQoK7RZVnXwWPg1KVbH3S9L1vb3 9SeIarcNejTlyHLgNHjFZqUlP6cYfBIzLTCjNOPJlSZBQETbaU4I0bgDz03llaByUmYf 2OK07G9ZTNO+E4uKz91xcHehSil2RRAlLx8Q+QWkusl+QRIrpdzIaWUhlm4UiEBNB6Jg 0AVQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689240816; x=1691832816; h=content-transfer-encoding:mime-version:message-id:date:subject:to :from:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=eqBl1zaWXmxGcAj53F4bE/yShI8TPZxujTgVO2UdhB4=; b=GlqI3ylXy0jB/zg9B00XI1hbV3NNyHDShAO2RjQbq3bY5qtMguqkCs2G5NXf2YIsBN Zf1g5/u0i8D5abys5I5/ONgcv/glxz7XaAOcqct86uwuxAEAr3ekAi5J6L2SeJZsXkcJ UuPmbMGH+t9Sp4bhkQijeCkKbznphaKBbxPFWI/FSL0VRhjZxItVGDHqgO/Ecv4DB67w X/LFYrEDNPOVBeWgoWXOBX0JA4yR3rROUlqvhkwly+GTaQ9W+ObfYq1w6mSuvQi0twZl R9UagPcrgOhIxjgG3PDYgnqIJEWr3cosqxvYDB16Zy87vJlyXBQrTqGP6dky+LND16qH 4AhA== X-Gm-Message-State: ABy/qLbj14/PiBb89dcbz77ivZxdct+HJ/07529XMocs/HskwKjPRmhl uQ/njoKJ5ewVk2a8cQR4uVF++tTHsNM8KDUmoW0= X-Google-Smtp-Source: APBJJlF8/BxGjHxFCGbVY6j+OlvIfQPlBqKboldpLD6qAlI7vjuuNZusp1f3zhGuO3izuIWYJd7UWQ== X-Received: by 2002:a17:902:cec6:b0:1b9:d38d:f08d with SMTP id d6-20020a170902cec600b001b9d38df08dmr6553825plg.18.1689240815798; Thu, 13 Jul 2023 02:33:35 -0700 (PDT) Return-Path: Received: from dhaval.blr.rivosinc.com ([49.249.129.34]) by smtp.gmail.com with ESMTPSA id d11-20020a170902b70b00b001b898595be7sm5431178pls.291.2023.07.13.02.33.34 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Jul 2023 02:33:35 -0700 (PDT) From: "Dhaval Sharma" To: devel@edk2.groups.io Subject: [PATCH v4 0/1] MdePkg:Implement RISCV CMO Date: Thu, 13 Jul 2023 15:03:30 +0530 Message-Id: <20230713093331.267164-1-dhaval@rivosinc.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Implementing code to support Cache Management Operations (CMO) defined by RV spec https://github.com/riscv/riscv-CMOs Notes: CMO only supports block based Operations. Meaning complete cache flush/invd/clean Operations are not available. In that case we fallback on fence.i instructions. Rely on the fact that platform init has initialized CMO and this implementation just checks if it is enabled. In order to avoid compiler dependency injecting byte code. Test: Ensured correct instructions are refelecting in asm Able to boot platform with RiscVVirtQemu config Not able to verify actual instruction in HW as Qemu ignores any actual cache operations. Dhaval Sharma (1): MdePkg:Implement RISCV CMO MdePkg/Library/BaseLib/BaseLib.inf | 2 +- MdePkg/Include/Register/RiscV64/RiscVEncoding.h | 4 + MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c | 200 ++++++++++++++++++-- MdePkg/Library/BaseLib/RiscV64/FlushCache.S | 21 -- MdePkg/Library/BaseLib/RiscV64/RiscVCacheMgmt.S | 64 +++++++ 5 files changed, 254 insertions(+), 37 deletions(-) delete mode 100644 MdePkg/Library/BaseLib/RiscV64/FlushCache.S create mode 100644 MdePkg/Library/BaseLib/RiscV64/RiscVCacheMgmt.S -- 2.34.1