From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pf1-f180.google.com (mail-pf1-f180.google.com [209.85.210.180]) by mx.groups.io with SMTP id smtpd.web10.3775.1689361713527427023 for ; Fri, 14 Jul 2023 12:08:33 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="signature has expired" header.i=@ventanamicro.com header.s=google header.b=Z3uO5cCz; spf=pass (domain: ventanamicro.com, ip: 209.85.210.180, mailfrom: tphan@ventanamicro.com) Received: by mail-pf1-f180.google.com with SMTP id d2e1a72fcca58-666ecb21f86so2188923b3a.3 for ; Fri, 14 Jul 2023 12:08:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1689361712; x=1691953712; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=7bYrP+zWArPLxDFpjIyqjZaiCBayod8yMijWQ30+Frk=; b=Z3uO5cCzuooGhqUm6RD5O7m1WcxjihCfkwxZm4eIn3la5sa0hCjYLuh1Jukot62bfC vMQCUqrVnJvI2BupWjWx/3D7JEF7+TncVD6Iw34wLrAXMVVXLIVvZAMq1iSzpiUHZU5K 1+tOsBuMDrG2YnZMsv3OEyhk7rHc9uvxzfcCOnFi4IHtQ8LpSEWig0SnofC5ps2YRyyI cjSyj+b9zjfcPmpYw31JhgKUW10V06n6c4A/D1BbAcKq4M9NkjKzvSzh0rNr+lJroqfB RjTpHEOZ1tdRexO6dKjU2z1m4rH1A8D0dd4hCc16LOuEwX4IbHeZKx6TcUNbfAjtjuVW Fs5g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689361712; x=1691953712; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=7bYrP+zWArPLxDFpjIyqjZaiCBayod8yMijWQ30+Frk=; b=D0LgiNht9fkkEheDNWDi8gMb21EMMogsmJV/fQzum+mPcmO84FzirQp1P9XS9pKO7C aUTgoGqvsq501Gt/h3i0aM0FwkFDXyk3qkEMFIW2R/4Y6ZS0O/UI2S6t8WahC2q0jcYW 8r3Wj+aerWjKd9iQTLDCqY/BUx7DcnkDWrB9/eeu4x/0YqVMYflHQyy7IFMddwrhFbLT 6Uum7zWoDrNFmqzvZUd9rGg387GzvpafTfr845jqMEVPZD8Fk76QCK7lYvbekn5O+h8W lkWZM6GOlqn498/6CgrrNGlKSFFBK9USrBDAI87fPf0K6Lj3VdNypzOJF5EeVT2RAJEH 530w== X-Gm-Message-State: ABy/qLYCvu5om5WI9knt/Nzfaq0SAoMABsvaRE6/pBBhvGfgnNjWZUff COKC/Rs4N+ayJ5eX3X5Rs+c06zh4H41JtPDMWHkSfg== X-Google-Smtp-Source: APBJJlHRY+H031tbEWrDRPDPYYjerQ1ayMyM/id/2utItLYY17wn37JeQmpQeaBoE+hAp/8HDvRCDw== X-Received: by 2002:a17:902:e852:b0:1b9:ea60:cd82 with SMTP id t18-20020a170902e85200b001b9ea60cd82mr5775861plg.5.1689361712439; Fri, 14 Jul 2023 12:08:32 -0700 (PDT) Return-Path: Received: from localhost.localdomain (c-174-50-177-95.hsd1.ca.comcast.net. [174.50.177.95]) by smtp.gmail.com with ESMTPSA id p18-20020a170902ead200b001a98f844e60sm8041413pld.263.2023.07.14.12.08.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Jul 2023 12:08:32 -0700 (PDT) From: "Tuan Phan" To: devel@edk2.groups.io Cc: michael.d.kinney@intel.com, gaoliming@byosoft.com.cn, zhiguang.liu@intel.com, sunilvl@ventanamicro.com, git@danielschaefer.me, andrei.warkentin@intel.com, ardb+tianocore@kernel.org, Tuan Phan Subject: [PATCH v5 0/7] Add RISC-V MMU support Date: Fri, 14 Jul 2023 12:08:17 -0700 Message-Id: <20230714190824.16552-1-tphan@ventanamicro.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit This series adds MMU support for RISC-V. Only SV39/48/57 modes are supported and tested. The MMU is required to support setting page attribute which is the first basic step to support security booting on RISC-V. There are two parts: 1. Add MMU base library. MMU will be enabled during CpuDxe initialization. 2. Fix all resources should be populated in HOB or added to GCD by driver before accessing when MMU enabled. All changes can be found in the branch tphan/riscv_mmu at: https://github.com/pttuan/edk2.git Changes in V5: - Rebased master. - Fix CI issue. Changes in v4: - Rebased master. - Added VirtNorFlashDxe to APRIORI DXE list. Changes in v3: - Move MMU library to UefiCpuPkg. - Add Andrei reviewed-by. Changes in v2: - Move MMU core to a library. - Setup SATP mode as highest possible that HW supports. Tuan Phan (7): MdePkg/BaseLib: RISC-V: Support getting satp register value MdePkg/Register: RISC-V: Add satp mode bits shift definition OvmfPkg/RiscVVirt: VirtNorFlashPlatformLib: Fix wrong flash size OvmfPkg/RiscVVirt: SEC: Add IO memory resource hob for platform devices OvmfPkg/RiscVVirt: Add VirtNorFlashDxe to APRIORI list OvmfPkg: RiscVVirt: Remove satp bare mode setting UefiCpuPkg: RISC-V: Support MMU with SV39/48/57 mode MdePkg/Include/Library/BaseLib.h | 5 + .../Include/Register/RiscV64/RiscVEncoding.h | 7 +- MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S | 8 + .../VirtNorFlashStaticLib.c | 3 +- OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc | 1 + OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf | 10 + OvmfPkg/RiscVVirt/Sec/Memory.c | 18 +- OvmfPkg/RiscVVirt/Sec/Platform.c | 62 ++ UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c | 9 +- UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h | 2 + UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf | 2 + UefiCpuPkg/Include/Library/BaseRiscVMmuLib.h | 68 ++ .../Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c | 730 ++++++++++++++++++ .../BaseRiscVMmuLib/BaseRiscVMmuLib.inf | 27 + .../Library/BaseRiscVMmuLib/RiscVMmuCore.S | 31 + UefiCpuPkg/UefiCpuPkg.dec | 5 + UefiCpuPkg/UefiCpuPkg.dsc | 1 + 17 files changed, 967 insertions(+), 22 deletions(-) create mode 100644 UefiCpuPkg/Include/Library/BaseRiscVMmuLib.h create mode 100644 UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c create mode 100644 UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf create mode 100644 UefiCpuPkg/Library/BaseRiscVMmuLib/RiscVMmuCore.S -- 2.25.1