From: "Tuan Phan" <tphan@ventanamicro.com>
To: devel@edk2.groups.io
Cc: michael.d.kinney@intel.com, gaoliming@byosoft.com.cn,
zhiguang.liu@intel.com, sunilvl@ventanamicro.com,
git@danielschaefer.me, andrei.warkentin@intel.com,
ardb+tianocore@kernel.org, Tuan Phan <tphan@ventanamicro.com>
Subject: [PATCH v5 2/7] MdePkg/Register: RISC-V: Add satp mode bits shift definition
Date: Fri, 14 Jul 2023 12:08:19 -0700 [thread overview]
Message-ID: <20230714190824.16552-3-tphan@ventanamicro.com> (raw)
In-Reply-To: <20230714190824.16552-1-tphan@ventanamicro.com>
The satp mode bits shift is used cross modules. It should be defined
in one place.
Signed-off-by: Tuan Phan <tphan@ventanamicro.com>
Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
---
MdePkg/Include/Register/RiscV64/RiscVEncoding.h | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/MdePkg/Include/Register/RiscV64/RiscVEncoding.h b/MdePkg/Include/Register/RiscV64/RiscVEncoding.h
index 5c2989b797bf..2bde8db478ff 100644
--- a/MdePkg/Include/Register/RiscV64/RiscVEncoding.h
+++ b/MdePkg/Include/Register/RiscV64/RiscVEncoding.h
@@ -58,9 +58,10 @@
#define PRV_S 1UL
#define PRV_M 3UL
-#define SATP64_MODE 0xF000000000000000ULL
-#define SATP64_ASID 0x0FFFF00000000000ULL
-#define SATP64_PPN 0x00000FFFFFFFFFFFULL
+#define SATP64_MODE 0xF000000000000000ULL
+#define SATP64_MODE_SHIFT 60
+#define SATP64_ASID 0x0FFFF00000000000ULL
+#define SATP64_PPN 0x00000FFFFFFFFFFFULL
#define SATP_MODE_OFF 0UL
#define SATP_MODE_SV32 1UL
--
2.25.1
next prev parent reply other threads:[~2023-07-14 19:08 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-14 19:08 [PATCH v5 0/7] Add RISC-V MMU support Tuan Phan
2023-07-14 19:08 ` [PATCH v5 1/7] MdePkg/BaseLib: RISC-V: Support getting satp register value Tuan Phan
2023-07-14 19:08 ` Tuan Phan [this message]
2023-07-14 19:08 ` [PATCH v5 3/7] OvmfPkg/RiscVVirt: VirtNorFlashPlatformLib: Fix wrong flash size Tuan Phan
2023-07-14 19:08 ` [PATCH v5 4/7] OvmfPkg/RiscVVirt: SEC: Add IO memory resource hob for platform devices Tuan Phan
2023-07-14 19:08 ` [PATCH v5 5/7] OvmfPkg/RiscVVirt: Add VirtNorFlashDxe to APRIORI list Tuan Phan
2023-07-14 19:08 ` [PATCH v5 6/7] OvmfPkg: RiscVVirt: Remove satp bare mode setting Tuan Phan
2023-07-14 19:08 ` [PATCH v5 7/7] UefiCpuPkg: RISC-V: Support MMU with SV39/48/57 mode Tuan Phan
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-list from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20230714190824.16552-3-tphan@ventanamicro.com \
--to=devel@edk2.groups.io \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox