From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pl1-f182.google.com (mail-pl1-f182.google.com [209.85.214.182]) by mx.groups.io with SMTP id smtpd.web10.3787.1689361728146287359 for ; Fri, 14 Jul 2023 12:08:48 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="signature has expired" header.i=@ventanamicro.com header.s=google header.b=TXyTH+ii; spf=pass (domain: ventanamicro.com, ip: 209.85.214.182, mailfrom: tphan@ventanamicro.com) Received: by mail-pl1-f182.google.com with SMTP id d9443c01a7336-1b890e2b9b7so13606435ad.3 for ; Fri, 14 Jul 2023 12:08:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1689361727; x=1691953727; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Vycf2C7PwHQ13XZ5mx2PsBAoCbBvYzSq88kCbMaz6qk=; b=TXyTH+iiWjaO7b1FDY/OlAvSdVQkNdaWb47MKcN8PYzJmy1vBt52YPXzsP5l02Gndk y8JF/1KCpljYQLWwKBz1OfbV9CG87OMsJx7tF3iXxIJ+WNLRJDYHgHzYztCn2O9GqLHc EyQdHtuWWHRa2ms2IS8bs8Zv8hDO/mCrvxfr+RzcftrkR0d+o1yk+dxSrD3gQD2dC1YD by+v0IyikRSg8/Av1kpEqnHNc/G4UFlN0NN9tfsFhFhr9fTdrYQBGOmktDhJBbF1o7S9 4XgFBmFmjjBgqt2zepd8jLgE/+KDBdZYeZGD8d6jVUHjV8Olu8ApyoQjYursiVptuLOf zRSA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689361727; x=1691953727; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Vycf2C7PwHQ13XZ5mx2PsBAoCbBvYzSq88kCbMaz6qk=; b=ZJXBE3Gvko588e4sJ4Sjthah7ZDa17GP5/5t56iaOQcKFnybrv9frymUpfSuzTAydd WLjW75CuaWY1X5z4Jqu4Y3JJXhoGsOCpU3XvCkSBvJCV56Ex1/2jMNyApIjO9JZSNlVv F5MJrJ1/oXpiXJMTbEM1zcGnI85jsZ9VTe6wbLo3oh6gFBD4wEsyXNGJk3JvF8O2uBZ9 gyfG7BvTJTz5VWLyPtJvegVmkyCyrrhq9Sm9slFbvtC99mo7s/zhbVfZLqpNx0FqJ5Sx F3+aArUd9J/QeR4yiUBiGPudhcfnZyKjdG3/Zq61kNd02OVTQZqfcfGFhCK+TMtnHdFZ Gj3w== X-Gm-Message-State: ABy/qLYoFd1rCG+xEf1GOLilC8pw/T3SDETvGWKWMZ3p/X7cO1HYv1be MBziXhzwhTCq79KSzNbsyRaF/WeAHJa6tpti5OjfVg== X-Google-Smtp-Source: APBJJlHNTv5K84WKuM7PMLvJY5v3/7GM8PsAPkIbN4NOQUG5TXCbRPyA1dhCwRgeCFy62Tpx67WSdA== X-Received: by 2002:a17:902:ec88:b0:1b7:fef7:d578 with SMTP id x8-20020a170902ec8800b001b7fef7d578mr4365522plg.41.1689361727203; Fri, 14 Jul 2023 12:08:47 -0700 (PDT) Return-Path: Received: from localhost.localdomain (c-174-50-177-95.hsd1.ca.comcast.net. [174.50.177.95]) by smtp.gmail.com with ESMTPSA id p18-20020a170902ead200b001a98f844e60sm8041413pld.263.2023.07.14.12.08.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Jul 2023 12:08:46 -0700 (PDT) From: "Tuan Phan" To: devel@edk2.groups.io Cc: michael.d.kinney@intel.com, gaoliming@byosoft.com.cn, zhiguang.liu@intel.com, sunilvl@ventanamicro.com, git@danielschaefer.me, andrei.warkentin@intel.com, ardb+tianocore@kernel.org, Tuan Phan Subject: [PATCH v5 2/7] MdePkg/Register: RISC-V: Add satp mode bits shift definition Date: Fri, 14 Jul 2023 12:08:19 -0700 Message-Id: <20230714190824.16552-3-tphan@ventanamicro.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230714190824.16552-1-tphan@ventanamicro.com> References: <20230714190824.16552-1-tphan@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable The satp mode bits shift is used cross modules. It should be defined in one place. Signed-off-by: Tuan Phan Reviewed-by: Andrei Warkentin Reviewed-by: Sunil V L Reviewed-by: Michael D Kinney --- MdePkg/Include/Register/RiscV64/RiscVEncoding.h | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/MdePkg/Include/Register/RiscV64/RiscVEncoding.h b/MdePkg/Inclu= de/Register/RiscV64/RiscVEncoding.h index 5c2989b797bf..2bde8db478ff 100644 --- a/MdePkg/Include/Register/RiscV64/RiscVEncoding.h +++ b/MdePkg/Include/Register/RiscV64/RiscVEncoding.h @@ -58,9 +58,10 @@ #define PRV_S 1UL=0D #define PRV_M 3UL=0D =0D -#define SATP64_MODE 0xF000000000000000ULL=0D -#define SATP64_ASID 0x0FFFF00000000000ULL=0D -#define SATP64_PPN 0x00000FFFFFFFFFFFULL=0D +#define SATP64_MODE 0xF000000000000000ULL=0D +#define SATP64_MODE_SHIFT 60=0D +#define SATP64_ASID 0x0FFFF00000000000ULL=0D +#define SATP64_PPN 0x00000FFFFFFFFFFFULL=0D =0D #define SATP_MODE_OFF 0UL=0D #define SATP_MODE_SV32 1UL=0D --=20 2.25.1