From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id A160C941405 for ; Wed, 19 Jul 2023 07:44:55 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=K7ntVgxuFLuK8lf6BvGPST/XgRLCe4WaLe3p2WzAUIg=; c=relaxed/simple; d=groups.io; h=X-Received:X-Received:X-IronPort-AV:X-IronPort-AV:X-Received:X-ExtLoop1:X-IronPort-AV:X-IronPort-AV:X-Received:From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References:MIME-Version:Precedence:List-Unsubscribe:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:X-Gm-Message-State:Content-Transfer-Encoding; s=20140610; t=1689752694; v=1; b=Av+F9Ur7NB+PAgKZhfqWc3geGNgT/RYkBeloV8kIezDKVVLOXBYk5fUZ9qDPhdInYqbHpiZP nJr4yyhi/9+vRNNovmehdRduYgzk8SdSf0em+PT2SteJQnad0SnJnNs1UEKyTXwANIaVi/bE5o2 NXGmnMigFP7fAd0UWcoPjnzk= X-Received: by 127.0.0.2 with SMTP id gpiCYY7687511xEpIPHDpFh1; Wed, 19 Jul 2023 00:44:54 -0700 X-Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by mx.groups.io with SMTP id smtpd.web11.8814.1689752689871664968 for ; Wed, 19 Jul 2023 00:44:53 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10775"; a="430163261" X-IronPort-AV: E=Sophos;i="6.01,216,1684825200"; d="scan'208";a="430163261" X-Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Jul 2023 00:44:53 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10775"; a="970515547" X-IronPort-AV: E=Sophos;i="6.01,216,1684825200"; d="scan'208";a="970515547" X-Received: from shwdeopenlab705.ccr.corp.intel.com ([10.239.55.55]) by fmsmga006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Jul 2023 00:44:51 -0700 From: "Yuanhao Xie" To: devel@edk2.groups.io Cc: Yuanhao Xie , Guo Dong , Ray Ni , Sean Rhodes , James Lu , Gua Guo Subject: [edk2-devel] [PATCH 1/4] UefiCpuPkg: Add SendStartupIpiAllExcludingSelf Date: Wed, 19 Jul 2023 15:44:32 +0800 Message-Id: <20230719074435.4331-2-yuanhao.xie@intel.com> In-Reply-To: <20230719074435.4331-1-yuanhao.xie@intel.com> References: <20230719074435.4331-1-yuanhao.xie@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,yuanhao.xie@intel.com X-Gm-Message-State: 7oie2hkSMtZkNvVbRD15Yu89x7686176AA= Content-Transfer-Encoding: 8bit X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=Av+F9Ur7; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=intel.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io From: Yuanhao Xie Add new API SendStartupIpiAllExcludingSelf(), and modify SendInitSipiSipiAllExcludingSelf() by let it call the new API. Cc: Guo Dong Cc: Ray Ni Cc: Sean Rhodes Cc: James Lu Cc: Gua Guo Signed-off-by: Yuanhao Xie --- UefiCpuPkg/Include/Library/LocalApicLib.h | 17 +++++++- .../Library/BaseXApicLib/BaseXApicLib.c | 43 +++++++++++++------ .../BaseXApicX2ApicLib/BaseXApicX2ApicLib.c | 43 +++++++++++++------ 3 files changed, 76 insertions(+), 27 deletions(-) diff --git a/UefiCpuPkg/Include/Library/LocalApicLib.h b/UefiCpuPkg/Include/Library/LocalApicLib.h index b55d88b0f5..d7c2ad3f70 100644 --- a/UefiCpuPkg/Include/Library/LocalApicLib.h +++ b/UefiCpuPkg/Include/Library/LocalApicLib.h @@ -4,7 +4,7 @@ Local APIC library assumes local APIC is enabled. It does not handles cases where local APIC is disabled. - Copyright (c) 2010 - 2019, Intel Corporation. All rights reserved.
+ Copyright (c) 2010 - 2023, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -185,6 +185,21 @@ SendInitIpiAllExcludingSelf ( VOID ); +/** + Send a Start-up IPI to all processors excluding self. + This function returns after the IPI has been accepted by the target processors. + if StartupRoutine >= 1M, then ASSERT. + if StartupRoutine is not multiple of 4K, then ASSERT. + @param StartupRoutine Points to a start-up routine which is below 1M physical + address and 4K aligned. +**/ + +VOID +EFIAPI +SendStartupIpiAllExcludingSelf ( + IN UINT32 StartupRoutine + ); + /** Send an INIT-Start-up-Start-up IPI sequence to a specified target processor. diff --git a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c index 008b8a070b..d56c6275cc 100644 --- a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c +++ b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c @@ -3,7 +3,7 @@ This local APIC library instance supports xAPIC mode only. - Copyright (c) 2010 - 2019, Intel Corporation. All rights reserved.
+ Copyright (c) 2010 - 2023, Intel Corporation. All rights reserved.
Copyright (c) 2017 - 2020, AMD Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent @@ -497,6 +497,33 @@ SendInitIpiAllExcludingSelf ( SendIpi (IcrLow.Uint32, 0); } +/** + Send a Start-up IPI to all processors excluding self. + This function returns after the IPI has been accepted by the target processors. + if StartupRoutine >= 1M, then ASSERT. + if StartupRoutine is not multiple of 4K, then ASSERT. + @param StartupRoutine Points to a start-up routine which is below 1M physical + address and 4K aligned. +**/ +VOID +EFIAPI +SendStartupIpiAllExcludingSelf ( + IN UINT32 StartupRoutine + ) +{ + LOCAL_APIC_ICR_LOW IcrLow; + + ASSERT (StartupRoutine < 0x100000); + ASSERT ((StartupRoutine & 0xfff) == 0); + + IcrLow.Uint32 = 0; + IcrLow.Bits.Vector = (StartupRoutine >> 12); + IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP; + IcrLow.Bits.Level = 1; + IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF; + SendIpi (IcrLow.Uint32, 0); +} + /** Send an INIT-Start-up-Start-up IPI sequence to a specified target processor. @@ -551,22 +578,12 @@ SendInitSipiSipiAllExcludingSelf ( IN UINT32 StartupRoutine ) { - LOCAL_APIC_ICR_LOW IcrLow; - - ASSERT (StartupRoutine < 0x100000); - ASSERT ((StartupRoutine & 0xfff) == 0); - SendInitIpiAllExcludingSelf (); MicroSecondDelay (PcdGet32 (PcdCpuInitIpiDelayInMicroSeconds)); - IcrLow.Uint32 = 0; - IcrLow.Bits.Vector = (StartupRoutine >> 12); - IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP; - IcrLow.Bits.Level = 1; - IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF; - SendIpi (IcrLow.Uint32, 0); + SendStartupIpiAllExcludingSelf (StartupRoutine); if (!StandardSignatureIsAuthenticAMD ()) { MicroSecondDelay (200); - SendIpi (IcrLow.Uint32, 0); + SendStartupIpiAllExcludingSelf (StartupRoutine); } } diff --git a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c index 0ba0499631..aa4eb11181 100644 --- a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c +++ b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c @@ -4,7 +4,7 @@ This local APIC library instance supports x2APIC capable processors which have xAPIC and x2APIC modes. - Copyright (c) 2010 - 2019, Intel Corporation. All rights reserved.
+ Copyright (c) 2010 - 2023, Intel Corporation. All rights reserved.
Copyright (c) 2017 - 2020, AMD Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent @@ -736,6 +736,33 @@ SendInitIpiAllExcludingSelf ( SendIpi (IcrLow.Uint32, 0); } +/** + Send a Start-up IPI to all processors excluding self. + This function returns after the IPI has been accepted by the target processors. + if StartupRoutine >= 1M, then ASSERT. + if StartupRoutine is not multiple of 4K, then ASSERT. + @param StartupRoutine Points to a start-up routine which is below 1M physical + address and 4K aligned. +**/ +VOID +EFIAPI +SendStartupIpiAllExcludingSelf ( + IN UINT32 StartupRoutine + ) +{ + LOCAL_APIC_ICR_LOW IcrLow; + + ASSERT (StartupRoutine < 0x100000); + ASSERT ((StartupRoutine & 0xfff) == 0); + + IcrLow.Uint32 = 0; + IcrLow.Bits.Vector = (StartupRoutine >> 12); + IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP; + IcrLow.Bits.Level = 1; + IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF; + SendIpi (IcrLow.Uint32, 0); +} + /** Send an INIT-Start-up-Start-up IPI sequence to a specified target processor. @@ -790,22 +817,12 @@ SendInitSipiSipiAllExcludingSelf ( IN UINT32 StartupRoutine ) { - LOCAL_APIC_ICR_LOW IcrLow; - - ASSERT (StartupRoutine < 0x100000); - ASSERT ((StartupRoutine & 0xfff) == 0); - SendInitIpiAllExcludingSelf (); MicroSecondDelay (PcdGet32 (PcdCpuInitIpiDelayInMicroSeconds)); - IcrLow.Uint32 = 0; - IcrLow.Bits.Vector = (StartupRoutine >> 12); - IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP; - IcrLow.Bits.Level = 1; - IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF; - SendIpi (IcrLow.Uint32, 0); + SendStartupIpiAllExcludingSelf (StartupRoutine); if (!StandardSignatureIsAuthenticAMD ()) { MicroSecondDelay (200); - SendIpi (IcrLow.Uint32, 0); + SendStartupIpiAllExcludingSelf (StartupRoutine); } } -- 2.36.1.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#107039): https://edk2.groups.io/g/devel/message/107039 Mute This Topic: https://groups.io/mt/100231360/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=-=-=-=-=-=-=-=-=-=-=-