From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id D1EAE7803E0 for ; Wed, 19 Jul 2023 12:09:01 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=6TJfoOe22X5O09OYWkRY4UxRGCmF0Drnbhx5B/BcfB8=; c=relaxed/simple; d=groups.io; h=X-Received:X-Received:X-Received:X-Virus-Scanned:X-Received:X-Received:From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References:MIME-Version:Precedence:List-Unsubscribe:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:X-Gm-Message-State:Content-Transfer-Encoding; s=20140610; t=1689768540; v=1; b=ZAya9d3dgtF2w9LzQxBiYsBQXUbvypT+kjWQKMlGr0ixkjrDlc2xGALbGR0uESIa1P7yGgkq UJts2Diy5Jkjk/6Dy+e+b+lutzv6wybigbO+3sbWcYNrmQ764g8m3bAcMP9F+UH1odazR3yNH3Z J85pvmBzUaBwev/LwIMCiD5Q= X-Received: by 127.0.0.2 with SMTP id 1wdcYY7687511xxqZZZwjiUY; Wed, 19 Jul 2023 05:09:00 -0700 X-Received: from muminek.juszkiewicz.com.pl (muminek.juszkiewicz.com.pl [213.251.184.221]) by mx.groups.io with SMTP id smtpd.web10.12042.1689768539310364325 for ; Wed, 19 Jul 2023 05:08:59 -0700 X-Received: from localhost (localhost [127.0.0.1]) by muminek.juszkiewicz.com.pl (Postfix) with ESMTP id 003AF26024A; Wed, 19 Jul 2023 14:08:56 +0200 (CEST) X-Virus-Scanned: Debian amavis at juszkiewicz.com.pl X-Received: from muminek.juszkiewicz.com.pl ([127.0.0.1]) by localhost (muminek.juszkiewicz.com.pl [127.0.0.1]) (amavis, port 10024) with ESMTP id e2kRnQTDFfLy; Wed, 19 Jul 2023 14:08:55 +0200 (CEST) X-Received: from applejack.lan (83.21.150.147.ipv4.supernova.orange.pl [83.21.150.147]) by muminek.juszkiewicz.com.pl (Postfix) with ESMTPSA id A974A26074E; Wed, 19 Jul 2023 14:08:54 +0200 (CEST) From: "Marcin Juszkiewicz" To: devel@edk2.groups.io Cc: Leif Lindholm , Ard Biesheuvel , Graeme Gregory , Shashi Mallela , Marcin Juszkiewicz Subject: [edk2-devel] [PATCH edk2-platforms v3 1/3] Platform/SbsaQemu: add GIC ITS support Date: Wed, 19 Jul 2023 14:08:40 +0200 Message-ID: <20230719120842.1120001-2-marcin.juszkiewicz@linaro.org> In-Reply-To: <20230719120842.1120001-1-marcin.juszkiewicz@linaro.org> References: <20230719120842.1120001-1-marcin.juszkiewicz@linaro.org> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,marcin.juszkiewicz@linaro.org X-Gm-Message-State: 6y3NOzBVthU63ZccxJOSrjpCx7686176AA= Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=ZAya9d3d; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=linaro.org (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io From: Shashi Mallela SBSA Reference Platform has GIC ITS support. Let make use of it. Base address is read from TF-A via SMC call. GIC ITS allows us to have complex PCI Express setups. Co-authored-by: Marcin Juszkiewicz Signed-off-by: Shashi Mallela Signed-off-by: Marcin Juszkiewicz --- Silicon/Qemu/SbsaQemu/SbsaQemu.dec | 3 + Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 3 + .../Qemu/SbsaQemu/AcpiTables/AcpiTables.inf | 2 + .../SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf | 1 + .../SbsaQemuPlatformDxe.inf | 1 + .../Include/IndustryStandard/SbsaQemuAcpi.h | 11 ++ .../Include/IndustryStandard/SbsaQemuSmc.h | 1 + .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 12 +- .../SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.c | 10 ++ Silicon/Qemu/SbsaQemu/AcpiTables/Iort.aslc | 135 ++++++++++++++++++ 10 files changed, 178 insertions(+), 1 deletion(-) create mode 100644 Silicon/Qemu/SbsaQemu/AcpiTables/Iort.aslc diff --git a/Silicon/Qemu/SbsaQemu/SbsaQemu.dec b/Silicon/Qemu/SbsaQemu/S= bsaQemu.dec index 5182978cf56d..ff2a4721a131 100644 --- a/Silicon/Qemu/SbsaQemu/SbsaQemu.dec +++ b/Silicon/Qemu/SbsaQemu/SbsaQemu.dec @@ -70,3 +70,6 @@ [PcdsDynamic.common] =20 gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformVersionMajor|0x0|UIN= T32|0x0000011E gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformVersionMinor|0x0|UIN= T32|0x0000011F + + # ARM Generic Interrupt Controller ITS + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdGicItsBase|0|UINT64|0x000001= 20 diff --git a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc b/Platform/Qemu/SbsaQemu= /SbsaQemu.dsc index b88729ad8ad6..4ae2479628b6 100644 --- a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc +++ b/Platform/Qemu/SbsaQemu/SbsaQemu.dsc @@ -523,6 +523,9 @@ [PcdsDynamicDefault.common] gArmTokenSpaceGuid.PcdGicDistributorBase|0x40060000 gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x40080000 =20 + # GIC ITS + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdGicItsBase|0 + # # Set video resolution for boot options # PlatformDxe can set the former at runtime. diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf b/Silicon/Qe= mu/SbsaQemu/AcpiTables/AcpiTables.inf index 0501c670d565..554c5e4b6f9e 100644 --- a/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf +++ b/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf @@ -22,6 +22,7 @@ [Sources] Gtdt.aslc Mcfg.aslc Spcr.aslc + Iort.aslc =20 [Packages] ArmPlatformPkg/ArmPlatformPkg.dec @@ -75,3 +76,4 @@ [FixedPcd] [Pcd] gArmTokenSpaceGuid.PcdGicDistributorBase gArmTokenSpaceGuid.PcdGicRedistributorsBase + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdGicItsBase diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDx= e.inf b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf index c1c33788567d..3ec7ffd8dd5c 100644 --- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf @@ -48,6 +48,7 @@ [Pcd] =20 gArmTokenSpaceGuid.PcdGicDistributorBase gArmTokenSpaceGuid.PcdGicRedistributorsBase + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdGicItsBase =20 [Depex] gEfiAcpiTableProtocolGuid ## CONSUMES diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPl= atformDxe.inf b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQem= uPlatformDxe.inf index 545794a8c7ff..0e3b11d60426 100644 --- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformD= xe.inf +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformD= xe.inf @@ -43,6 +43,7 @@ [Pcd] =20 gArmTokenSpaceGuid.PcdGicDistributorBase gArmTokenSpaceGuid.PcdGicRedistributorsBase + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdGicItsBase =20 =20 [Depex] diff --git a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.= h b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h index 853b81b34df5..983d17f6fa50 100644 --- a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h +++ b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h @@ -27,6 +27,7 @@ #define SBSAQEMU_MADT_GIC_HBASE 0x2c010000 #define SBSAQEMU_MADT_GIC_PMU_IRQ 23 #define SBSAQEMU_MADT_GICR_SIZE 0x4000000 +#define SBSAQEMU_MADT_GITS_SIZE 0x20000 =20 // Macro for MADT GIC Redistributor Structure #define SBSAQEMU_MADT_GICR_INIT() { = \ @@ -37,6 +38,16 @@ SBSAQEMU_MADT_GICR_SIZE /* DiscoveryRangeLength */ = \ } =20 +// Macro for MADT GIC ITS Structure +#define SBSAQEMU_MADT_GIC_ITS_INIT(GicItsId) { = \ + EFI_ACPI_6_5_GIC_ITS, /* Type */ = \ + sizeof (EFI_ACPI_6_5_GIC_ITS_STRUCTURE), /* Length */ = \ + EFI_ACPI_RESERVED_WORD, /* Reserved */ = \ + GicItsId, /* GicItsId */ = \ + PcdGet64 (PcdGicItsBase), /* PhysicalBaseAddress */ = \ + EFI_ACPI_RESERVED_DWORD /* Reserved2 */ = \ + } + #define SBSAQEMU_ACPI_SCOPE_OP_MAX_LENGTH 5 =20 #define SBSAQEMU_ACPI_SCOPE_NAME { '_', 'S', 'B', '_' } diff --git a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h= b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h index 7fbd3bd887d0..7934875e4aba 100644 --- a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h +++ b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h @@ -13,5 +13,6 @@ =20 #define SIP_SVC_VERSION SMC_SIP_FUNCTION_ID(1) #define SIP_SVC_GET_GIC SMC_SIP_FUNCTION_ID(100) +#define SIP_SVC_GET_GIC_ITS SMC_SIP_FUNCTION_ID(101) =20 #endif /* SBSA_QEMU_SMC_H_ */ diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDx= e.c b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c index ae5397bab768..961482269678 100644 --- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c @@ -91,6 +91,11 @@ AddMadtTable ( // Initialize GIC Redistributor Structure EFI_ACPI_6_0_GICR_STRUCTURE Gicr =3D SBSAQEMU_MADT_GICR_INIT(); =20 + // Initialize GIC ITS Structure + EFI_ACPI_6_5_GIC_ITS_STRUCTURE Gic_Its =3D SBSAQEMU_MADT_GIC_ITS_INIT(= 0); + + DEBUG ((DEBUG_ERROR, "itsBaseAddr is 0x%4x\n", PcdGet64 (PcdGicItsBase= ))); + // Get CoreCount which was determined eariler after parsing device tre= e NumCores =3D PcdGet32 (PcdCoreCount); =20 @@ -98,7 +103,8 @@ AddMadtTable ( TableSize =3D sizeof (EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEA= DER) + (sizeof (EFI_ACPI_6_0_GIC_STRUCTURE) * NumCores) + sizeof (EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE) + - sizeof (EFI_ACPI_6_0_GICR_STRUCTURE); + sizeof (EFI_ACPI_6_0_GICR_STRUCTURE) + + sizeof (EFI_ACPI_6_5_GIC_ITS_STRUCTURE); =20 Status =3D gBS->AllocatePages ( AllocateAnyPages, @@ -138,6 +144,10 @@ AddMadtTable ( CopyMem (New, &Gicr, sizeof (EFI_ACPI_6_0_GICR_STRUCTURE)); New +=3D sizeof (EFI_ACPI_6_0_GICR_STRUCTURE); =20 + // GIC ITS Structure + CopyMem (New, &Gic_Its, sizeof (EFI_ACPI_6_5_GIC_ITS_STRUCTURE)); + New +=3D sizeof (EFI_ACPI_6_5_GIC_ITS_STRUCTURE); + AcpiPlatformChecksum ((UINT8*) PageAddress, TableSize); =20 Status =3D AcpiTable->InstallAcpiTable ( diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPl= atformDxe.c b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuP= latformDxe.c index f6a3e84483fe..ddcca2b7243c 100644 --- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformD= xe.c +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformD= xe.c @@ -86,5 +86,15 @@ InitializeSbsaQemuPlatformDxe ( =20 DEBUG ((DEBUG_INFO, "GICR base: 0x%x\n", Arg0)); =20 + SmcResult =3D ArmCallSmc0 (SIP_SVC_GET_GIC_ITS, &Arg0, NULL, NULL); + if (SmcResult =3D=3D SMC_ARCH_CALL_SUCCESS) { + Result =3D PcdSet64S (PcdGicItsBase, Arg0); + ASSERT_RETURN_ERROR (Result); + } + + Arg0 =3D PcdGet64 (PcdGicItsBase); + + DEBUG ((DEBUG_INFO, "GICI base: 0x%x\n", Arg0)); + return EFI_SUCCESS; } diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/Iort.aslc b/Silicon/Qemu/Sb= saQemu/AcpiTables/Iort.aslc new file mode 100644 index 000000000000..ec4ce504efd1 --- /dev/null +++ b/Silicon/Qemu/SbsaQemu/AcpiTables/Iort.aslc @@ -0,0 +1,135 @@ +/** @file + + Copyright (c) 2023, Linaro Ltd. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include + +#pragma pack(1) + +typedef struct { + EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE Node; + UINT32 Identifiers; +} SBSA_EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE; + +typedef struct +{ + EFI_ACPI_6_0_IO_REMAPPING_SMMU3_NODE SmmuNode; + EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE SmmuIdMap; +} SBSA_EFI_ACPI_6_0_IO_REMAPPING_SMMU3_NODE; + +typedef struct +{ + EFI_ACPI_6_0_IO_REMAPPING_RC_NODE RcNode; + EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE RcIdMap; +} SBSA_EFI_ACPI_6_0_IO_REMAPPING_RC_NODE; + +typedef struct { + EFI_ACPI_6_0_IO_REMAPPING_TABLE Iort; + SBSA_EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE ItsNode; + SBSA_EFI_ACPI_6_0_IO_REMAPPING_SMMU3_NODE SmmuNode; + SBSA_EFI_ACPI_6_0_IO_REMAPPING_RC_NODE RcNode; +} SBSA_IO_REMAPPING_STRUCTURE; + +#pragma pack () + +STATIC SBSA_IO_REMAPPING_STRUCTURE Iort =3D { + { + SBSAQEMU_ACPI_HEADER(EFI_ACPI_6_0_IO_REMAPPING_TABLE_SIGNATURE, + SBSA_IO_REMAPPING_STRUCTURE, + EFI_ACPI_IO_REMAPPING_TABLE_REVISION_00), + 3, // NumNodes + sizeof(EFI_ACPI_6_0_IO_REMAPPING_TABLE), // NodeOffset + 0 // Reserved + }, + // SBSA_EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE + { + // EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE + { + // EFI_ACPI_6_0_IO_REMAPPING_NODE + { + EFI_ACPI_IORT_TYPE_ITS_GROUP, // Type + sizeof (SBSA_EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE), // Length + 0, // Revision + 0, // Reserved + 0, // NumIdMappings + 0, // IdReference + }, + 1, // ITS count + }, + 0, // GIC ITS Identifiers + }, + // SMMU + { + // EFI_ACPI_6_0_IO_REMAPPING_SMMU3_NODE + { + // EFI_ACPI_6_0_IO_REMAPPING_NODE + { + EFI_ACPI_IORT_TYPE_SMMUv3, // Type + sizeof (SBSA_EFI_ACPI_6_0_IO_REMAPPING_SMMU3_NODE), // Length + 2, // Revision + 0, // Reserved + 1, // NumIdMapping + OFFSET_OF (SBSA_EFI_ACPI_6_0_IO_REMAPPING_SMMU3_NODE, SmmuIdMap)= , // IdReference + }, + 0x60050000, // Base address + EFI_ACPI_IORT_SMMUv3_FLAG_COHAC_OVERRIDE, // Flags + 0, // Reserved + 0, // VATOS address + EFI_ACPI_IORT_SMMUv3_MODEL_GENERIC, // SMMUv3 Model + 74, // Event + 75, // Pri + 77, // Gerror + 76, // Sync + 0, // Proximity domain + 1, // DevIDMappingIndex + }, + // EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE + { + 0x0000, // InputBase + 0xffff, // NumIds + 0x0000, // OutputBase + OFFSET_OF (SBSA_IO_REMAPPING_STRUCTURE, ItsNode), // OutputRefer= ence + 0, // Flags + }, + }, + // SBSA_EFI_ACPI_6_0_IO_REMAPPING_RC_NODE + { + // EFI_ACPI_6_0_IO_REMAPPING_RC_NODE + { + // EFI_ACPI_6_0_IO_REMAPPING_NODE + { + EFI_ACPI_IORT_TYPE_ROOT_COMPLEX, // Type + sizeof (SBSA_EFI_ACPI_6_0_IO_REMAPPING_RC_NODE), // Length + 0, // Revision + 0, // Reserved + 1, // NumIdMappings + OFFSET_OF (SBSA_EFI_ACPI_6_0_IO_REMAPPING_RC_NODE, RcIdMap) // = IdReference + }, + 1, // CacheCoherent + 0, // AllocationHints + 0, // Reserved + 0, // MemoryAccessFlags + EFI_ACPI_IORT_ROOT_COMPLEX_ATS_UNSUPPORTED, // AtsAttribute + 0x0, // PciSegmentNumber + //0, //MemoryAddressSizeLimit + }, + // EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE + { + 0x0000, // InputBase + 0xffff, // NumIds + 0x0000, // OutputBase + OFFSET_OF (SBSA_IO_REMAPPING_STRUCTURE, SmmuNode), // OutputRefer= ence + 0, // Flags + } + } +}; + +#pragma pack() + +VOID* CONST ReferenceAcpiTable =3D &Iort; \ No newline at end of file --=20 2.41.0 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#107050): https://edk2.groups.io/g/devel/message/107050 Mute This Topic: https://groups.io/mt/100233783/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=-=-=-=-=-=-=-=-=-=-=-