From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id EEE877803D2 for ; Mon, 24 Jul 2023 20:15:31 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=wXqigEiQiiht/WZHUTrxWVXO2cg7vu1A/9TQxsVmsfc=; c=relaxed/simple; d=groups.io; h=X-Received:X-Received:X-Received:X-Gm-Message-State:X-Google-Smtp-Source:X-Received:X-Received:From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Transfer-Encoding; s=20140610; t=1690229730; v=1; b=LH4J2Ueg1Q2JqG9YsFPnqamgDL2mu3jX9UBRae5jeE3agC1u2/O49WqxBhkJWVe/eW+ZoclT YLtdvUJ9C5BfLyVms+p/Nwpa9S24UfpTViISQRWmKc5jIKwXtixf6IJDFSLRI5bC+3E0UnvsT4g 8t1IRIcWPPSkSevsZlJPKNLg= X-Received: by 127.0.0.2 with SMTP id AtMUYY7687511xeaw1q7M8iy; Mon, 24 Jul 2023 13:15:30 -0700 X-Received: from mail-pl1-f170.google.com (mail-pl1-f170.google.com [209.85.214.170]) by mx.groups.io with SMTP id smtpd.web11.4786.1690229729646798215 for ; Mon, 24 Jul 2023 13:15:29 -0700 X-Received: by mail-pl1-f170.google.com with SMTP id d9443c01a7336-1bb2468257fso24875155ad.0 for ; Mon, 24 Jul 2023 13:15:29 -0700 (PDT) X-Gm-Message-State: iwZbhvAqiBWxC2toSzeh1m6px7686176AA= X-Google-Smtp-Source: APBJJlHQRAMNYWgT21txRmrkFpH7JaUKhW42QPsOghV43iz3IHvSgiYIlDeMGSxIT5mie+LoYGg+lw== X-Received: by 2002:a17:903:2445:b0:1b8:a7ec:38c5 with SMTP id l5-20020a170903244500b001b8a7ec38c5mr10297210pls.57.1690229728762; Mon, 24 Jul 2023 13:15:28 -0700 (PDT) X-Received: from MININT-0U7P5GU.redmond.corp.microsoft.com ([2001:4898:80e8:0:18a3:9b95:e44:14fd]) by smtp.gmail.com with ESMTPSA id y7-20020a1709029b8700b001b89045ff03sm9398104plp.233.2023.07.24.13.15.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Jul 2023 13:15:28 -0700 (PDT) From: "Kun Qin" To: devel@edk2.groups.io Cc: Leif Lindholm , Ard Biesheuvel , Sami Mujawar Subject: [edk2-devel] [PATCH v1 2/3] ArmPkg: ArmGicLib: Added GIC v3 and v4 support to ArmGicSendSgiTo Date: Mon, 24 Jul 2023 13:15:21 -0700 Message-ID: <20230724201523.852-3-kuqin12@gmail.com> In-Reply-To: <20230724201523.852-1-kuqin12@gmail.com> References: <20230724201523.852-1-kuqin12@gmail.com> MIME-Version: 1.0 Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,kuqin12@gmail.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=LH4J2Ueg; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=gmail.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io From: Kun Qin REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4466 This change extended the existing function `ArmGicSendSgiTo` of ArmGicLib to format the incoming parameters to comply with GICv3 and GICv4 spec, and signal software generated interrupts to non secure group 1 at EL1. Cc: Leif Lindholm Cc: Ard Biesheuvel Cc: Sami Mujawar Signed-off-by: Kun Qin --- ArmPkg/Drivers/ArmGic/ArmGicLib.c | 52 +++++++++++++++++--- ArmPkg/Include/Library/ArmGicLib.h | 22 +++++++++ 2 files changed, 68 insertions(+), 6 deletions(-) diff --git a/ArmPkg/Drivers/ArmGic/ArmGicLib.c b/ArmPkg/Drivers/ArmGic/ArmG= icLib.c index 7f4bb248fc72..830d822d2c05 100644 --- a/ArmPkg/Drivers/ArmGic/ArmGicLib.c +++ b/ArmPkg/Drivers/ArmGic/ArmGicLib.c @@ -146,12 +146,52 @@ ArmGicSendSgiTo ( IN UINT8 SgiId=0D )=0D {=0D - MmioWrite32 (=0D - GicDistributorBase + ARM_GIC_ICDSGIR,=0D - ((TargetListFilter & 0x3) << 24) |=0D - ((CPUTargetList & 0xFF) << 16) |=0D - (SgiId & 0xF)=0D - );=0D + ARM_GIC_ARCH_REVISION Revision;=0D + UINT32 ApplicableTargets;=0D + UINT32 AFF3;=0D + UINT32 AFF2;=0D + UINT32 AFF1;=0D + UINT32 AFF0;=0D + UINT32 Irm;=0D + UINT64 SGIValue;=0D +=0D + Revision =3D ArmGicGetSupportedArchRevision ();=0D + if (Revision =3D=3D ARM_GIC_ARCH_REVISION_2) {=0D + MmioWrite32 (=0D + GicDistributorBase + ARM_GIC_ICDSGIR,=0D + ((TargetListFilter & 0x3) << 24) |=0D + ((CPUTargetList & 0xFF) << 16) |=0D + (SgiId & 0xF)=0D + );=0D + } else {=0D + // Below routine is adopted from gicv3_raise_secure_g0_sgi in TF-A=0D +=0D + /* Extract affinity fields from target */=0D + AFF0 =3D GET_MPIDR_AFF0 (CPUTargetList);=0D + AFF1 =3D GET_MPIDR_AFF1 (CPUTargetList);=0D + AFF2 =3D GET_MPIDR_AFF2 (CPUTargetList);=0D + AFF3 =3D GET_MPIDR_AFF3 (CPUTargetList);=0D +=0D + /*=0D + * Make target list from affinity 0, and ensure GICv3 SGI can target=0D + * this PE.=0D + */=0D + ApplicableTargets =3D (1 << AFF0);=0D +=0D + /*=0D + * Evaluate the filter to see if this is for the target or all others= =0D + */=0D + Irm =3D (TargetListFilter =3D=3D ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE) = ? SGIR_IRM_TO_OTHERS : SGIR_IRM_TO_AFF;=0D +=0D + /* Raise SGI to PE specified by its affinity */=0D + SGIValue =3D GICV3_SGIR_VALUE (AFF3, AFF2, AFF1, SgiId, Irm, Applicabl= eTargets);=0D +=0D + /*=0D + * Ensure that any shared variable updates depending on out of band=0D + * interrupt trigger are observed before raising SGI.=0D + */=0D + ArmGicV3SendNsG1Sgi (SGIValue);=0D + }=0D }=0D =0D /*=0D diff --git a/ArmPkg/Include/Library/ArmGicLib.h b/ArmPkg/Include/Library/Ar= mGicLib.h index 773b27954522..28d58f187d4f 100644 --- a/ArmPkg/Include/Library/ArmGicLib.h +++ b/ArmPkg/Include/Library/ArmGicLib.h @@ -110,6 +110,28 @@ // Bit Mask for=0D #define ARM_GIC_ICCIAR_ACKINTID 0x3FF=0D =0D +/* ICC SGI macros */=0D +#define SGIR_TGT_MASK ((UINT64)0xffff)=0D +#define SGIR_AFF1_SHIFT 16=0D +#define SGIR_INTID_SHIFT 24=0D +#define SGIR_INTID_MASK ((UINT64)0xf)=0D +#define SGIR_AFF2_SHIFT 32=0D +#define SGIR_IRM_SHIFT 40=0D +#define SGIR_IRM_MASK ((UINT64)0x1)=0D +#define SGIR_AFF3_SHIFT 48=0D +#define SGIR_AFF_MASK ((UINT64)0xff)=0D +=0D +#define SGIR_IRM_TO_AFF 0=0D +#define SGIR_IRM_TO_OTHERS 1=0D +=0D +#define GICV3_SGIR_VALUE(_aff3, _aff2, _aff1, _intid, _irm, _tgt) \=0D + ((((UINT64) (_aff3) & SGIR_AFF_MASK) << SGIR_AFF3_SHIFT) | \=0D + (((UINT64) (_irm) & SGIR_IRM_MASK) << SGIR_IRM_SHIFT) | \=0D + (((UINT64) (_aff2) & SGIR_AFF_MASK) << SGIR_AFF2_SHIFT) | \=0D + (((_intid) & SGIR_INTID_MASK) << SGIR_INTID_SHIFT) | \=0D + (((_aff1) & SGIR_AFF_MASK) << SGIR_AFF1_SHIFT) | \=0D + ((_tgt) & SGIR_TGT_MASK))=0D +=0D UINT32=0D EFIAPI=0D ArmGicGetInterfaceIdentification (=0D --=20 2.41.0.windows.2 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. 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